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Adam
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- fpu_latch... returns enum of result type
- added FGetStat and FSetStat to set ns32081 status register
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-64
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+91
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‎src/mame/tektronix/tek440x.cpp

+91-64
Original file line numberDiff line numberDiff line change
@@ -498,6 +498,12 @@ namespace {
498498
PHASE_NEGATIVE
499499
};
500500

501+
enum {
502+
FLOATRESULT=0,
503+
DOUBLERESULT=1,
504+
INTRESULT=2
505+
};
506+
501507
class tek440x_state : public driver_device
502508
{
503509
public:
@@ -567,8 +573,10 @@ class tek440x_state : public driver_device
567573
void mouse_w(u8 data);
568574
void led_w(u8 data);
569575

570-
void fpu_latch32_result(void *);
571-
void fpu_latch64_result(void *);
576+
int fpu_latch32_result(void *);
577+
int fpu_latch64_result(void *);
578+
int fpu_latch32_int_result(void *);
579+
572580
u16 fpu_r(offs_t offset);
573581
void fpu_w(offs_t offset, u16 data);
574582
u16 videoaddr_r(offs_t offset);
@@ -646,6 +654,7 @@ class tek440x_state : public driver_device
646654
bool m_kb_loop;
647655

648656
u16 m_fpuselect;
657+
u16 m_fpustatus;
649658
u16 m_operand;
650659
u16 m_lswoperand[5];
651660
u16 m_mswoperand[5];
@@ -1011,8 +1020,6 @@ void tek440x_state::mapcntl_w(u8 data)
10111020

10121021
}
10131022

1014-
enum {FLOATRESULT=0, DOUBLERESULT=1, INTRESULT=2};
1015-
10161023
enum {
10171024
FPCALC = 0xbe,
10181025
FPCONV = 0x3e,
@@ -1052,7 +1059,7 @@ enum {
10521059

10531060
void tek440x_state::fpu_w(offs_t offset, u16 data)
10541061
{
1055-
LOG("fpu_w: %08x <= 0x%04x\n", offset, data);
1062+
//LOGMASKED(LOG_FPU,"fpu_w: %08x <= 0x%04x\n", offset, data);
10561063

10571064
switch(offset)
10581065
{
@@ -1069,26 +1076,34 @@ void tek440x_state::fpu_w(offs_t offset, u16 data)
10691076
m_operand++;
10701077
break;
10711078

1072-
// start op, can be FPCALC or FPCONV...
1079+
// start op, can be FPCALC or FPCONV...possibly
10731080
case 6:
1074-
m_result = 0;
10751081
m_fpuselect = data;
1082+
m_result = 0;
10761083
m_operand = 0;
10771084
break;
10781085
case 7:
10791086
break;
10801087
}
10811088
}
10821089

1083-
void tek440x_state::fpu_latch32_result(void *v)
1090+
int tek440x_state::fpu_latch32_result(void *v)
10841091
{
10851092
m_result <<= 32;
10861093
m_result |= *(uint32_t *)v;
1094+
return FLOATRESULT;
10871095
}
10881096

1089-
void tek440x_state::fpu_latch64_result(void *v)
1097+
int tek440x_state::fpu_latch64_result(void *v)
10901098
{
10911099
m_result = *(uint64_t *)v;
1100+
return DOUBLERESULT;
1101+
}
1102+
1103+
int tek440x_state::fpu_latch32_int_result(void *v)
1104+
{
1105+
fpu_latch32_result(v);
1106+
return INTRESULT;
10921107
}
10931108

10941109
#define CASE_ENUM(C) case C: opname = #C; break
@@ -1105,6 +1120,29 @@ u16 tek440x_state::fpu_r(offs_t offset)
11051120
uint32_t v32;
11061121
uint64_t v64;
11071122

1123+
// assembling operands
1124+
if (m_operand >= 2) // has at least 1 32-bit operands
1125+
{
1126+
v32 = (m_mswoperand[1] << 16) | (m_lswoperand[1]);
1127+
ai = v32;
1128+
af = *(float *)&v32;
1129+
1130+
if (m_operand >= 3) // has at least 2 32-bit operands or 1 64-bit operand
1131+
{
1132+
v32 = (m_mswoperand[2] << 16) | (m_lswoperand[2]);
1133+
bf = *(float *)&v32;
1134+
1135+
v64 = (((uint64_t)m_mswoperand[2]) << 48) | (((uint64_t)m_lswoperand[2])<<32) | (((uint64_t)m_mswoperand[1]) << 16) | (m_lswoperand[1]);
1136+
ad = *(double *)&v64;
1137+
}
1138+
1139+
if (m_operand == 5) // has 2 64-bit operands
1140+
{
1141+
v64 = (((uint64_t)m_mswoperand[4]) << 48) | (((uint64_t)m_lswoperand[4])<<32) | (((uint64_t)m_mswoperand[3]) << 16) | (m_lswoperand[3]);
1142+
bd = *(double *)&v64;
1143+
}
1144+
}
1145+
11081146
#ifdef DEBUG
11091147
const char *opname;
11101148
switch(m_lswoperand[0])
@@ -1138,36 +1176,15 @@ u16 tek440x_state::fpu_r(offs_t offset)
11381176
break;
11391177
}
11401178
LOGMASKED(LOG_FPU,"fpu_r: %s ************** %s \n", m_fpuselect == FPCALC ? "FPCALC" : "FPCONV", opname);
1179+
1180+
LOGMASKED(LOG_FPU,"fpu_r: m_operand(%d) float(%f) int(%d)\n", m_operand, af, ai);
1181+
if (m_operands >= 3)
1182+
LOGMASKED(LOG_FPU,"fpu_r: m_operand(%d) float(%f) float(%f) double(%lf) 0x%lx\n", m_operand, af,bf, ad, v64);
1183+
if (m_operands >= 5)
1184+
LOGMASKED(LOG_FPU,"fpu_r: m_operand(%d) double(%lf) double(%lf)\n", m_operand, ad,bd);
11411185
#endif
11421186

1143-
// assembling operands
1144-
if (m_operand >= 2) // has at least 1 32-bit operands
1145-
{
1146-
v32 = (m_mswoperand[1] << 16) | (m_lswoperand[1]);
1147-
ai = v32;
1148-
af = *(float *)&v32;
1149-
LOGMASKED(LOG_FPU,"fpu_r: m_operand(%d) float(%f) int(%d)\n", m_operand, af, ai);
1150-
1151-
if (m_operand >= 3) // has at least 2 32-bit operands or 1 64-bit operand
1152-
{
1153-
v32 = (m_mswoperand[2] << 16) | (m_lswoperand[2]);
1154-
bf = *(float *)&v32;
1155-
1156-
v64 = (((uint64_t)m_mswoperand[2]) << 48) | (((uint64_t)m_lswoperand[2])<<32) | (((uint64_t)m_mswoperand[1]) << 16) | (m_lswoperand[1]);
1157-
ad = *(double *)&v64;
1158-
1159-
LOGMASKED(LOG_FPU,"fpu_r: m_operand(%d) float(%f) float(%f) double(%lf) 0x%lx\n", m_operand, af,bf, ad, v64);
1160-
}
1161-
1162-
if (m_operand == 5) // has 2 64-bit operands
1163-
{
1164-
v64 = (((uint64_t)m_mswoperand[4]) << 48) | (((uint64_t)m_lswoperand[4])<<32) | (((uint64_t)m_mswoperand[3]) << 16) | (m_lswoperand[3]);
1165-
bd = *(double *)&v64;
11661187

1167-
LOGMASKED(LOG_FPU,"fpu_r: m_operand(%d) double(%lf) double(%lf)\n", m_operand, ad,bd);
1168-
}
1169-
}
1170-
11711188
// execute the functionality
11721189
int resulttype = FLOATRESULT;
11731190
int ci;
@@ -1177,128 +1194,138 @@ u16 tek440x_state::fpu_r(offs_t offset)
11771194
{
11781195
case FADD:
11791196
cf = bf + af;
1180-
fpu_latch32_result(&cf);
1181-
resulttype = FLOATRESULT;
1197+
resulttype = fpu_latch32_result(&cf);
1198+
FLOATRESULT;
11821199
break;
11831200
case FSUB:
11841201
cf = bf - af;
1185-
fpu_latch32_result(&cf);
1202+
resulttype = fpu_latch32_result(&cf);
11861203
resulttype = FLOATRESULT;
11871204
break;
11881205
case FMUL:
11891206
cf = bf * af;
1190-
fpu_latch32_result(&cf);
1207+
resulttype = fpu_latch32_result(&cf);
11911208
resulttype = FLOATRESULT;
11921209
break;
11931210
case FDIV:
11941211
cf = bf / af;
1195-
fpu_latch32_result(&cf);
1212+
resulttype = fpu_latch32_result(&cf);
11961213
resulttype = FLOATRESULT;
11971214
break;
11981215
case FCMP:
11991216
ci = af > bf ? 1 : (af < bf ? -1 : 0);
1200-
fpu_latch32_result(&ci);
1217+
resulttype = fpu_latch32_result(&ci);
12011218
resulttype = FLOATRESULT;
12021219
break;
12031220

12041221
case FNEG:
12051222
cf = -af;
1206-
fpu_latch32_result(&cf);
1223+
resulttype = fpu_latch32_result(&cf);
12071224
resulttype = FLOATRESULT;
12081225
break;
12091226
case FABS:
12101227
cf = fabs(af);
1211-
fpu_latch32_result(&cf);
1228+
resulttype = fpu_latch32_result(&cf);
12121229
resulttype = FLOATRESULT;
12131230
break;
12141231

12151232
case FItoF:
12161233
cf = (float)ai;
1217-
fpu_latch32_result(&cf);
1234+
resulttype = fpu_latch32_result(&cf);
12181235
resulttype = FLOATRESULT;
12191236
break;
12201237
case FFtoIr:
12211238
ci = (int)(af + 0.5f);
1222-
fpu_latch32_result(&ci);
1239+
resulttype = fpu_latch32_int_result(&ci);
12231240
resulttype = INTRESULT;
12241241
break;
12251242
case FFtoIt:
12261243
ci = (int)(af);
1227-
fpu_latch32_result(&ci);
1244+
resulttype = fpu_latch32_int_result(&ci);
12281245
resulttype = INTRESULT;
12291246
break;
12301247
case FFtoIf:
12311248
ci = (int)floorf(af);
1232-
fpu_latch32_result(&ci);
1249+
resulttype = fpu_latch32_int_result(&ci);
12331250
resulttype = INTRESULT;
12341251
break;
12351252

12361253
case FFtoD:
12371254
cd = (double)af;
1238-
fpu_latch64_result(&cd);
1255+
resulttype = fpu_latch64_result(&cd);
12391256
resulttype = DOUBLERESULT;
12401257
break;
12411258
case FDtoF:
12421259
cf = (float)ad;
1243-
fpu_latch32_result(&cf);
1260+
resulttype = fpu_latch32_result(&cf);
1261+
resulttype = FLOATRESULT;
12441262
break;
12451263

12461264
case DADD:
12471265
cd = bd + ad;
1248-
fpu_latch64_result(&cd);
1266+
resulttype = fpu_latch64_result(&cd);
12491267
resulttype = DOUBLERESULT;
12501268
break;
12511269
case DSUB:
12521270
cd = bd - ad;
1253-
fpu_latch64_result(&cd);
1271+
resulttype = fpu_latch64_result(&cd);
12541272
resulttype = DOUBLERESULT;
12551273
break;
12561274
case DMUL:
12571275
cd = bd * ad;
1258-
fpu_latch64_result(&cd);
1276+
resulttype = fpu_latch64_result(&cd);
12591277
resulttype = DOUBLERESULT;
12601278
break;
12611279
case DDIV:
12621280
cd = bd / ad;
1263-
fpu_latch64_result(&cd);
1281+
resulttype = fpu_latch64_result(&cd);
12641282
resulttype = DOUBLERESULT;
12651283
break;
12661284
case DCMP:
12671285
ci = ad > bd ? 1 : (ad < bd ? -1 : 0);
1268-
fpu_latch32_result(&ci);
1286+
resulttype = fpu_latch32_result(&ci);
12691287
resulttype = DOUBLERESULT;
12701288
break;
12711289

12721290
case DNEG:
12731291
cd = -ad;
1274-
fpu_latch64_result(&cd);
1292+
resulttype = fpu_latch64_result(&cd);
12751293
resulttype = DOUBLERESULT;
12761294
break;
12771295
case DABS:
12781296
cd = fabs(ad);
1279-
fpu_latch64_result(&cd);
1297+
resulttype = fpu_latch64_result(&cd);
12801298
resulttype = DOUBLERESULT;
12811299
break;
12821300

12831301
case FItoD:
12841302
cd = (double)ai;
1285-
fpu_latch64_result(&cd);
1303+
resulttype = fpu_latch64_result(&cd);
12861304
resulttype = DOUBLERESULT;
12871305
break;
12881306
case FDtoIr:
12891307
ci = (int)(ad + 0.5);
1290-
fpu_latch32_result(&ci);
1291-
resulttype = DOUBLERESULT;
1308+
resulttype = fpu_latch32_int_result(&ci);
1309+
resulttype = INTRESULT;
12921310
break;
12931311
case FDtoIt:
12941312
ci = (int)(ad);
1295-
fpu_latch32_result(&ci);
1296-
resulttype = DOUBLERESULT;
1313+
resulttype = fpu_latch32_int_result(&ci);
1314+
resulttype = INTRESULT;
12971315
break;
12981316
case FDtoIf:
12991317
ci = (int)floor(ad);
1300-
fpu_latch32_result(&ci);
1301-
resulttype = DOUBLERESULT;
1318+
resulttype = fpu_latch32_int_result(&ci);
1319+
resulttype = INTRESULT;
1320+
break;
1321+
1322+
case GETS:
1323+
ai = m_fpustatus;
1324+
resulttype = fpu_latch32_int_result(&ai);
1325+
break;
1326+
case SETS:
1327+
m_fpustatus = ai;
1328+
resulttype = fpu_latch32_int_result(&ai);
13021329
break;
13031330

13041331
default:

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