@@ -1200,8 +1200,7 @@ u8 sprinter_state::m1_r(offs_t offset)
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if (!machine ().side_effects_disabled ())
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{
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- if (!m_prf_d)
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- m_in_out_cmd = (data & 0xf7 ) == 0xd3 ; // d3/db
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+ m_in_out_cmd = !m_prf_d && (data & 0xf7 ) == 0xd3 ; // d3/db - only non-prefixed
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accel_control_r (data);
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}
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@@ -1262,8 +1261,12 @@ void sprinter_state::init_taps()
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{
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if (!machine ().side_effects_disabled ())
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{
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- if (!m_z80_m1 && m_in_out_cmd && data == 0x1f )
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- data = 0x0f ;
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+ if (m_in_out_cmd && !m_z80_m1)
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+ {
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+ if (data == 0x1f && (m_pages[BIT (offset, 14 , 2 )] & BANK_RAM_MASK))
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+ data = 0x0f ;
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+ m_in_out_cmd = false ;
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+ }
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if (!(m_pages[BIT (offset, 14 , 2 )] & (BANK_FASTRAM_MASK | BANK_ISA_MASK))) // ROM+RAM
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do_cpu_wait ();
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if (!m_z80_m1 && acc_ena () && (m_acc_dir != OFF))
@@ -1272,8 +1275,12 @@ void sprinter_state::init_taps()
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});
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prg.install_write_tap (0x10000 , 0x1ffff , " accel_write" , [this ](offs_t offset, u8 &data, u8 mem_mask)
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{
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- if (!m_z80_m1 && m_in_out_cmd && data == 0x1f )
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- data = 0x0f ;
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+ if (m_in_out_cmd && !m_z80_m1)
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+ {
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+ if (data == 0x1f && (m_pages[BIT (offset, 14 , 2 )] & BANK_RAM_MASK))
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+ data = 0x0f ;
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+ m_in_out_cmd = false ;
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+ }
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if (!(m_pages[BIT (offset, 14 , 2 )] & 0xff00 )) // ROM only, RAM(w) applies waits manually
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do_cpu_wait ();
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if (!m_z80_m1 && acc_ena () && (m_acc_dir != OFF))
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