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Adam
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- easier to read logging of MMU state changes
- comment out log of every memory_r and memory_w
1 parent ee3acf6 commit e5e8a25

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+83
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+83
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‎src/mame/tektronix/tek440x.cpp

+83-52
Original file line numberDiff line numberDiff line change
@@ -124,7 +124,7 @@ class m68010_tekmmu_device : public m68010_device
124124
LOG("map_r: bus error: PID(%d) %08x fc(%d) pc(%08x)\n", BIT(m_map[(offset >> 11) & 0x7ff], 11, 3), OFF16_TO_OFF8(offset), get_fc(), pc());
125125
set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
126126
set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
127-
set_buserror_details(offset, 0, get_fc());
127+
set_buserror_details(offset, true, get_fc());
128128
return 0;
129129
}
130130
}
@@ -155,9 +155,9 @@ class m68010_tekmmu_device : public m68010_device
155155
{
156156
// page 2.1-54 implies that this can only be read in user mode
157157

158-
LOGMASKED(LOG_MMU, "mapcntl_r(%02x) cpuWr(%d) BlockAccess(%d) SysWrEn(%d) PID(%d) pc(%08x)\n",m_map_control,
159-
BIT(m_map_control, MAP_CPU_WR) ? 1 : 0,
160-
BIT(m_map_control, MAP_BLOCK_ACCESS) ? 1 : 0,
158+
LOGMASKED(LOG_MMU, "mapcntl_r(%02x) cpuWr(%s) BlockAccess(%s) SysWrEn(%d) PID(%d) pc(%08x)\n",m_map_control,
159+
BIT(m_map_control, MAP_CPU_WR) ? "WRITE" : "READ",
160+
BIT(m_map_control, MAP_BLOCK_ACCESS) ? "NO" : "YES",
161161
BIT(m_map_control, MAP_SYS_WR_ENABLE) ? 1 : 0,
162162
m_map_control & 15,
163163
pc());
@@ -176,7 +176,7 @@ class m68010_tekmmu_device : public m68010_device
176176
void mapcntl_w(u8 data)
177177
{
178178
// copied on user mode read/write
179-
m_latched_map_control = data & 0x3f;
179+
m_latched_map_control = (data & 0x3f);
180180

181181
if (m_map_control != m_latched_map_control)
182182
{
@@ -336,7 +336,7 @@ class m68010_tekmmu_device : public m68010_device
336336
if (!BIT(*m_map_control_ptr, MAP_SYS_WR_ENABLE))
337337
{
338338
LOG("PTEread: bus error: PID(%d) %08x fc(%d) pc(%08x)\n", BIT(m_map_ptr[(address >> 12) & 0x7ff], 11, 3), (address), get_fc(), pc());
339-
set_buserror_details(address, 1, get_fc(), false);
339+
set_buserror_details(address, true, get_fc(), false);
340340
set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
341341
set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
342342
return 0;
@@ -726,7 +726,6 @@ void tek440x_state::machine_reset()
726726
m_u244latch = 0;
727727
m_led_disk = 1;
728728
m_keyboard->kdo_w(1);
729-
m_latched_map_control = 0;
730729
mapcntl_w(0);
731730
videocntl_w(0);
732731
videoaddr_w(0,0);
@@ -789,22 +788,22 @@ u16 tek440x_state::memory_r(offs_t offset, u16 mem_mask)
789788
{
790789
if ((m_maincpu->get_fc() & 4) == 0) // User mode access updates map_control from write latch
791790
{
792-
if (m_latched_map_control != (m_map_control & 0x3f))
791+
if ((m_latched_map_control & 0x1f) != (m_map_control & 0x1f))
793792
{
794793
LOG("memory_r: m_map_control updated 0x%04x\n", m_latched_map_control);
795-
m_map_control &= ~0x3f;
796-
m_map_control |= m_latched_map_control;
797794
}
795+
m_map_control &= ~0x1f;
796+
m_map_control |= (m_latched_map_control & 0x1f);
798797
}
799798

800799
const offs_t offset0 = offset;
801800

802801
#ifndef USE_MMU
803802
if (!inbuserr) // not in buserr interrupt
804803
if ((m_maincpu->get_fc() & 4) == 0) // only in User mode
805-
if (BIT(m_map_control, MAP_VM_ENABLE))
804+
if (BIT(m_map_control, MAP_VM_ENABLE) )
806805
{
807-
806+
808807
// is !cpuWr
809808
m_map_control &= ~(1 << MAP_CPU_WR);
810809

@@ -813,15 +812,17 @@ u16 tek440x_state::memory_r(offs_t offset, u16 mem_mask)
813812
{
814813
m_map_control &= ~(1 << MAP_BLOCK_ACCESS);
815814

815+
// FIXME: if this is a prefetch, it will be cancelled in src/devices/cpu/m68000/m68kcpu.h, but we've changed m_map_control..
816+
816817
inbuserr = 1;
817818

818-
LOG("memory_r: %06x: bus error: PTE PID %d != current PID %d fc(%d) pc(%08x) berr(%d)\n", offset<<1,
819+
LOG("memory_r: %06x: bus error: PTE_PID(%d) != mapcntl_PID(%d) fc(%d) pc(%08x) berr(%d) map_control(%02x) latch(%02x)\n", offset<<1,
819820
BIT(m_map[offset >> 11], 11, 3), (m_map_control & 7), m_maincpu->get_fc(), m_maincpu->pc(),
820-
inbuserr);
821-
m_maincpu->set_buserror_details(OFF16_TO_OFF8(offset0), 1, m_maincpu->get_fc(), true);
821+
inbuserr, m_map_control, m_latched_map_control);
822+
m_maincpu->set_buserror_details(OFF16_TO_OFF8(offset0), true, m_maincpu->get_fc(), true);
822823

823824
mem_mask = 0;
824-
return 0xffff;
825+
return 0;
825826

826827
}
827828
else
@@ -838,14 +839,14 @@ u16 tek440x_state::memory_r(offs_t offset, u16 mem_mask)
838839
// NB byte memory limit, offset is *word* offset
839840
if (offset >= OFF8_TO_OFF16(MAXRAM) && offset < OFF8_TO_OFF16(0x600000))
840841
{
841-
LOG("memory_r: bus error: NOMEM %08x fc(%d) pc(%08x)\n", OFF16_TO_OFF8(offset), m_maincpu->get_fc(), m_maincpu->pc());
842-
m_maincpu->set_buserror_details(OFF16_TO_OFF8(offset0), 1, m_maincpu->get_fc(), true);
842+
LOG("memory_r: %08x bus error: NOMEM fc(%d) pc(%08x)\n", OFF16_TO_OFF8(offset), m_maincpu->get_fc(), m_maincpu->pc());
843+
m_maincpu->set_buserror_details(OFF16_TO_OFF8(offset0), true, m_maincpu->get_fc(), true);
843844
}
844845
}
845846

846847
if (inbuserr && (m_maincpu->get_fc() & 4))
847848
{
848-
LOG("berr reset(r) %06x\n", offset<<1);
849+
LOG("berr reset(r) %06x\n", OFF16_TO_OFF8(offset));
849850
inbuserr = 0;
850851
}
851852

@@ -856,53 +857,62 @@ void tek440x_state::memory_w(offs_t offset, u16 data, u16 mem_mask)
856857
{
857858
if ((m_maincpu->get_fc() & 4) == 0) // User mode access updates map_control from write latch
858859
{
859-
if (m_latched_map_control != (m_map_control & 0x3f))
860+
if ((m_latched_map_control & 0x1f) != (m_map_control & 0x1f))
860861
{
861862
LOG("memory_w: m_map_control updated 0x%04x\n", m_latched_map_control);
862-
m_map_control &= ~0x3f;
863-
m_map_control |= m_latched_map_control;
864863
}
864+
m_map_control &= ~0x1f;
865+
m_map_control |= (m_latched_map_control & 0x1f);
865866
}
866867

867868
const offs_t offset0 = offset;
869+
868870
#ifndef USE_MMU
869871
if ((m_maincpu->get_fc() & 4) == 0) // only in User mode
870872
if (BIT(m_map_control, MAP_VM_ENABLE))
871873
{
872874
//LOG("memory_w: m_map(0x%04x)\n", m_map[offset >> 11]);
873875

874876
// is cpuWr
875-
m_map_control |= (1 << MAP_CPU_WR);
877+
if (!inbuserr)
878+
m_map_control |= (1 << MAP_CPU_WR);
876879

877880
// matching pid?
878881
if ( (BIT(m_map[offset >> 11], 11, 3) != (m_map_control & 7)))
879882
{
880-
// NB active low
881-
m_map_control &= ~(1 << MAP_BLOCK_ACCESS);
883+
if (!inbuserr)
884+
{
885+
// NB active low
886+
m_map_control &= ~(1 << MAP_BLOCK_ACCESS);
882887

883-
inbuserr = 1;
888+
LOG("memory_w: %06x bus error: PTE_PID(%d) != mapcntl_PID(%d) fc(%d)\n", OFF16_TO_OFF8(offset), BIT(m_map[offset >> 11], 11, 3), (m_map_control & 7), m_maincpu->get_fc());
889+
m_maincpu->set_buserror_details(OFF16_TO_OFF8(offset0), false, m_maincpu->get_fc(), true);
890+
}
884891

885-
LOG("memory_w: bus error: PID(%d) != %d %08x fc(%d)\n", BIT(m_map[offset >> 11], 11, 3), (m_map_control & 7), OFF16_TO_OFF8(offset), m_maincpu->get_fc());
886-
m_maincpu->set_buserror_details(OFF16_TO_OFF8(offset0), 0, m_maincpu->get_fc(), true);
887-
888-
mem_mask = 0; // disable write
892+
inbuserr = 1;
889893
}
890894
else if (!inbuserr)
891895
{
892896
m_map_control |= (1 << MAP_BLOCK_ACCESS);
893897
}
894-
else mem_mask = 0;
898+
899+
if (inbuserr)
900+
mem_mask = 0; // disable write
895901

896902
// write-enabled page?
897903
if (mem_mask)
898904
if (BIT(m_map[offset >> 11], 14) == 0)
899905
{
900906
m_map_control &= ~(1 << MAP_BLOCK_ACCESS);
907+
908+
// is this right?
909+
m_map_control &= ~(1 << MAP_SYS_WR_ENABLE);
910+
901911

902912
inbuserr = 1;
903913

904-
LOG("memory_w: bus error: READONLY %08x fc(%d) pc(%08x)\n", OFF16_TO_OFF8(offset), m_maincpu->get_fc(), m_maincpu->pc());
905-
m_maincpu->set_buserror_details(OFF16_TO_OFF8(offset0), 0, m_maincpu->get_fc(), true);
914+
LOG("memory_w: %06x bus error: READONLY fc(%d) pc(%08x)\n", OFF16_TO_OFF8(offset), m_maincpu->get_fc(), m_maincpu->pc());
915+
m_maincpu->set_buserror_details(OFF16_TO_OFF8(offset0), false, m_maincpu->get_fc(), true);
906916

907917
mem_mask = 0; // disable write
908918
return;
@@ -912,10 +922,13 @@ void tek440x_state::memory_w(offs_t offset, u16 data, u16 mem_mask)
912922
if (mem_mask)
913923
{
914924
if (!(m_map[offset >> 11] & 0x8000))
915-
LOG("memory_w: DIRTY m_map(0x%04x) m_map_control(%02x) berr(%d)\n", m_map[offset >> 11], m_map_control, inbuserr);
925+
LOG("memory_w: DIRTY m_map(0x%04x) m_map_control(%02x) berr(%d) fc(%d)\n", m_map[offset >> 11], m_map_control, inbuserr, m_maincpu->get_fc());
916926
m_map[offset >> 11] |= 0x8000;
917927
}
918928

929+
//if (mem_mask)
930+
// LOG("memory_w: map %08x => paddr(%08x) berr(%d) fc(%d) pc(%08x)\n",OFF16_TO_OFF8(offset), OFF16_TO_OFF8(BIT(offset, 0, 11) | BIT(m_map[offset >> 11], 0, 11) << 11), inbuserr, m_maincpu->get_fc(), m_maincpu->pc());
931+
919932
offset = BIT(offset, 0, 11) | (BIT(m_map[offset >> 11], 0, 11) << 11);
920933
}
921934
#endif
@@ -924,12 +937,12 @@ void tek440x_state::memory_w(offs_t offset, u16 data, u16 mem_mask)
924937
if (offset >= OFF8_TO_OFF16(MAXRAM) && offset < OFF8_TO_OFF16(0x600000) && !machine().side_effects_disabled())
925938
{
926939
LOG("memory_w: bus error: NOMEM %08x fc(%d)\n", OFF16_TO_OFF8(offset), m_maincpu->get_fc());
927-
m_maincpu->set_buserror_details(OFF16_TO_OFF8(offset0), 0, m_maincpu->get_fc(), true);
940+
m_maincpu->set_buserror_details(OFF16_TO_OFF8(offset0), false, m_maincpu->get_fc(), true);
928941
}
929942

930943
if (inbuserr && (m_maincpu->get_fc() & 4))
931944
{
932-
LOG("berr reset(w) %06x\n", offset<<1);
945+
LOG("berr reset(w) %06x\n", OFF16_TO_OFF8(offset));
933946
inbuserr = 0;
934947
}
935948

@@ -941,13 +954,16 @@ u16 tek440x_state::map_r(offs_t offset)
941954
if (!machine().side_effects_disabled())
942955
{
943956
if ((offset>>11) < 0x20)
957+
{
944958
LOGMASKED(LOG_MMU, "map_r 0x%08x => %04x\n",offset>>11, m_map[(offset >> 11)&0x7ff] );
959+
}
945960

946961
// selftest does a read and expects it to fail iff !MAP_SYS_WR_ENABLE; its not WR enable, its enable..
947-
if (!BIT(m_map_control, MAP_SYS_WR_ENABLE))
962+
// NB page 2.1-52 shows WrMapEn coming from latch
963+
if (!BIT(m_latched_map_control, MAP_SYS_WR_ENABLE))
948964
{
949965
LOGMASKED(LOG_MMU, "map_r: bus error: PID(%d) %08x fc(%d) pc(%08x)\n", BIT(m_map[(offset >> 11) & 0x7ff], 11, 3), OFF16_TO_OFF8(offset), m_maincpu->get_fc(), m_maincpu->pc());
950-
m_maincpu->set_buserror_details(offset, 1, m_maincpu->get_fc(), true);
966+
m_maincpu->set_buserror_details(offset, true, m_maincpu->get_fc(), true);
951967
return 0;
952968
}
953969
}
@@ -970,6 +986,10 @@ void tek440x_state::map_w(offs_t offset, u16 data, u16 mem_mask)
970986
{
971987
COMBINE_DATA(&m_map[(offset >> 11) & 0x7ff]);
972988
}
989+
else
990+
{
991+
LOGMASKED(LOG_MMU, "map_w: %08x !MAP_SYS_WR_ENABLE\n", (offset >> 11) & 0x7ff);
992+
}
973993
}
974994

975995
u8 tek440x_state::mapcntl_r()
@@ -978,10 +998,11 @@ u8 tek440x_state::mapcntl_r()
978998
{
979999
// page 2.1-54 implies that this can only be read in user mode
9801000

981-
LOG("mapcntl_r(%02x) cpuWr(%d) BlockAccess(%d) SysWrEn(%d) PID(%d) pc(%08x)\n",m_map_control,
982-
BIT(m_map_control, MAP_CPU_WR) ? 1 : 0,
983-
BIT(m_map_control, MAP_BLOCK_ACCESS) ? 1 : 0,
1001+
LOG("mapcntl_r(%02x) cpuWr(%s) BlockAccess(%s) SysWrEn(%d) VMenable(%d) PID(%d) pc(%08x)\n",m_map_control,
1002+
BIT(m_map_control, MAP_CPU_WR) ? "WRITE" : "READ",
1003+
BIT(m_map_control, MAP_BLOCK_ACCESS) ? "NO" : "YES",
9841004
BIT(m_map_control, MAP_SYS_WR_ENABLE) ? 1 : 0,
1005+
BIT(m_map_control, MAP_VM_ENABLE) ? 1 : 0,
9851006
m_map_control & 15,
9861007
m_maincpu->pc());
9871008

@@ -1000,22 +1021,31 @@ u8 tek440x_state::mapcntl_r()
10001021
void tek440x_state::mapcntl_w(u8 data)
10011022
{
10021023
// copied on user mode read/write
1003-
m_latched_map_control = data & 0x3f;
1024+
m_latched_map_control = (data & 0x3f);
10041025

1005-
if (m_map_control != m_latched_map_control)
1026+
if ((m_map_control & 0x1f) != (m_latched_map_control & 0x1f))
10061027
{
1007-
LOGMASKED(LOG_MMU, "mapcntl_w(%02x) cpuWr(%d) BlockAccess(%d) SysWrEn(%d) PID(%d) pc(%08x)\n",m_latched_map_control,
1008-
BIT(m_latched_map_control, MAP_CPU_WR) ? 1 : 0,
1009-
BIT(m_latched_map_control, MAP_BLOCK_ACCESS) ? 1 : 0,
1010-
BIT(m_latched_map_control, MAP_SYS_WR_ENABLE) ? 1 : 0,
1011-
m_latched_map_control & 15,
1012-
m_maincpu->pc());
1028+
LOGMASKED(LOG_MMU, "mapcntl_w(%02x) ",m_latched_map_control);
1029+
if (BIT(m_latched_map_control, MAP_SYS_WR_ENABLE) != BIT(m_map_control, MAP_SYS_WR_ENABLE))
1030+
{
1031+
LOGMASKED(LOG_MMU, "SysWrEn(%d => %d) ", BIT(m_map_control, MAP_SYS_WR_ENABLE), BIT(m_latched_map_control, MAP_SYS_WR_ENABLE));
1032+
}
1033+
if (BIT(m_latched_map_control, MAP_VM_ENABLE) != BIT(m_map_control, MAP_VM_ENABLE))
1034+
{
1035+
LOGMASKED(LOG_MMU, "VMenable(%d => %d) ", BIT(m_map_control, MAP_VM_ENABLE), BIT(m_latched_map_control, MAP_VM_ENABLE));
1036+
}
1037+
if ((m_latched_map_control & 15) != (m_map_control & 15))
1038+
{
1039+
LOGMASKED(LOG_MMU, "PID(%d => %d) ", (m_map_control & 15),(m_latched_map_control & 15));
1040+
}
1041+
LOGMASKED(LOG_MMU, " pc(%08x)\n", m_maincpu->pc());
10131042

1043+
if (0)
10141044
if (BIT(data, MAP_VM_ENABLE) && (data & 15))
10151045
for(uint32_t i=0; i<2048; i++)
10161046
{
10171047
if (m_map[i])
1018-
LOGMASKED(LOG_MMU, "XXXmapcntl_w: %08x -> paddr(%08x) PID(%d) dirty(%d) write_enable(%d)\n",
1048+
LOGMASKED(LOG_MMU, "mapcntl_w: %08x -> paddr(%08x) PID(%d) dirty(%d) write_enable(%d)\n",
10191049
OFF16_TO_OFF8(i << 11), OFF16_TO_OFF8(BIT(m_map[i], 0, 11)<<11),
10201050
BIT(m_map[i], 11, 3), m_map[i] & 0x8000 ? 1 : 0, m_map[i] & 0x4000 ? 1 : 0);
10211051
}
@@ -1025,7 +1055,8 @@ void tek440x_state::mapcntl_w(u8 data)
10251055
// NB bit 6 & 7 is not used
10261056

10271057
// disable using latched state below
1028-
//m_map_control = data & 0x3f;
1058+
m_map_control &= 0xc0;
1059+
m_map_control |= m_latched_map_control;
10291060

10301061
}
10311062

@@ -1085,7 +1116,7 @@ u16 tek440x_state::fpu_r(offs_t offset)
10851116
if (m_fpu_finished)
10861117
{
10871118
result = m_fpu->slow_status();
1088-
//LOGMASKED(LOG_FPU,"fpu_r: status = 0x%04x\n", result);
1119+
LOGMASKED(LOG_FPU,"fpu_r: status = 0x%04x\n", result);
10891120
}
10901121
else
10911122
{

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