Reduce Triton TBE unweighted backward reduction width (#4488) - #4488
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Reduce Triton TBE unweighted backward reduction width (#4488)#4488stashuk-olek wants to merge 5 commits into
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Summary: Use BoundsCheckMode.V2 for Triton TBE standalone index validation. This preserves the existing warning and offset-repair behavior while reducing validation overhead before Triton forward. Reviewed By: axeisghost, TroyGarden Differential Revision: D114279989
Summary: Validate and repair indices inside supported unweighted, non-VBE Triton forward kernels. Unsupported configurations retain the CUDA v2 fallback, while fused checked loads preserve warning accumulation without a separate full-index pass. Reviewed By: TroyGarden, axeisghost Differential Revision: D114284802
Summary: Restructure short- and long-run gradient accumulation to reduce serialized reduction pressure. The new reduction schedule exposes more independent work while preserving the existing exact rowwise optimizer update. Reviewed By: axeisghost Differential Revision: D114273026
) Summary: Reduce the dout reduction tile from 16 to 8 in the unweighted short-run, separate long-run accumulation, and fused long-run kernels. The smaller tile reduces live vector state and register pressure on B200 while retaining FP32 accumulation and the existing rowwise optimizer update. Weighted kernels remain unchanged. Reviewed By: axeisghost Differential Revision: D114403703
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) Summary: Reduce the dout reduction tile from 16 to 8 in the unweighted short-run, separate long-run accumulation, and fused long-run kernels. The smaller tile reduces live vector state and register pressure on B200 while retaining FP32 accumulation and the existing rowwise optimizer update. Weighted kernels remain unchanged. Reviewed By: axeisghost Differential Revision: D114403703
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) Summary: Reduce the dout reduction tile from 16 to 8 in the unweighted short-run, separate long-run accumulation, and fused long-run kernels. The smaller tile reduces live vector state and register pressure on B200 while retaining FP32 accumulation and the existing rowwise optimizer update. Weighted kernels remain unchanged. Reviewed By: axeisghost Differential Revision: D114403703
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) Summary: Reduce the dout reduction tile from 16 to 8 in the unweighted short-run, separate long-run accumulation, and fused long-run kernels. The smaller tile reduces live vector state and register pressure on B200 while retaining FP32 accumulation and the existing rowwise optimizer update. Weighted kernels remain unchanged. Reviewed By: axeisghost Differential Revision: D114403703
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) Summary: Reduce the dout reduction tile from 16 to 8 in the unweighted short-run, separate long-run accumulation, and fused long-run kernels. The smaller tile reduces live vector state and register pressure on B200 while retaining FP32 accumulation and the existing rowwise optimizer update. Weighted kernels remain unchanged. Reviewed By: axeisghost Differential Revision: D114403703
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Summary:
Reduce the dout reduction tile from 16 to 8 in the unweighted short-run, separate long-run accumulation, and fused long-run kernels. The smaller tile reduces live vector state and register pressure on B200 while retaining FP32 accumulation and the existing rowwise optimizer update. Weighted kernels remain unchanged.
Reviewed By: axeisghost
Differential Revision: D114403703