This repository provides three MPLAB® X projects for interfacing the Configurable Logic Block (CLB) and I/O Ports peripherals with a 7-segment display to show hexadecimal numbers:
- 7-Segment Display Decoder With LUTs
- 7-Segment Display Decoder With Logic Gates
- 7-Segment Display Decoder With Verilog HDL
The CLB peripheral is a collection of logic elements that can be programmed to perform a wide variety of digital logic functions. The logic function may be completely combinational, sequential, or a mix of the two, enabling users to incorporate hardware-based custom logic into their applications.
More details and code examples on the PIC16F13276 can be found at the following links:
- PIC16F13276 Product Page
- PIC16F13276 Code Examples on Discover
- PIC16F13276 Code Examples on GitHub
- 7-Segment Display Data Sheet
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7-Segment Display
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7 x 330 ohm Resistors
To program the Curiosity Nano board with this MPLAB X project, follow the steps provided in the How to Program the Curiosity Nano Board chapter.
This example demonstrates the capabilities of the CLB, a Core Independent Peripheral (CIP), that can control and manipulate the transmitted data through the I/O Ports for the Software Input register of the CLB (CLBSWIN). The software application generates a numeric value from 0 to 15, then writes it into the CLBSWIN register via the CLB1_SWIN_Write8() function. The CLB module decodes the four-bit data into a seven-bit word, each corresponding to an LED segment. The result is a series of hexadecimal digits shown sequentially on the display.
This application includes three different solutions through the CLB peripheral:
- Use seven different Look-up Table (LUT) embedded circuits for each pin of the display.
- Use only logic gates: AND, NOT, OR.
- Use the Hardware Description Language (HDL) to implement combinational logic.
All implementations lead to the same result. The used display is Common Cathode, where all the cathode connections of the LED segments are connected together to logic '0' or ground. The separate segments are lightened by applying the logic '1' or HIGH signal through a current limiting resistor to forward bias the individual anode terminals a to g, as shown below.
The table below presents the truth table that correctly displays the hexadecimal number on a 7-segment display, depending on the input values.
| In | Out | Displayed Symbol | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SWIN3 | SWIN2 | SWIN1 | SWIN0 | g | f | e | d | c | b | a | ||
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | |
| 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 2 | |
| 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 3 | |
| 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 4 | |
| 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 5 | |
| 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 6 | |
| 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 7 | |
| 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 8 | |
| 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 9 | |
| 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | A | |
| 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | b | |
| 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | C | |
| 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | d | |
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | E | |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | F |
All three projects implement the combinational logic of the 7-segment decoder using the CLB peripheral, but in three different manners. The main idea of the application is to display all the hexadecimal values on a 7-segment display, using software data from the main project interfaced with the CLB.
The first project is described by seven LUT circuits as seen in the figure below. Each LUT corresponds to one of the inputs of the 7-segment display, called from a to f, and its value is '1' or '0', according to the table above.
The second project is defined by having the CLB only configure logic gates (NOT, AND, OR), which implies a higher complexity level compared to the first project. Each final output of the logic gates corresponds to one of the inputs of the 7-segment display, called from a to f, and its value is '1' or '0', according to the table above.
The third project uses an HDL module, implemented in Verilog, as shown below.
The four inputs are grouped as a 4-bit bus, named i.
The seven outputs are grouped as a 7-bit bus, named o.
A combinational logic, implemented as a case statement within an always block sensitive to all signals of the bus i, is inserted in between.
The Verilog code is reproduced below.
module display_hdl(i0, i1, i2, i3, o0, o1, o2, o3, o4, o5, o6);
input i0, i1, i2, i3;
output o0, o1, o2, o3, o4, o5, o6;
reg [6:0]o;
reg [3:0]i;
assign i = {i3, i2, i1, i0};
always @(*) begin
case(i) // gfedcba
4'h0: o = 7'b0111111; // 0
4'h1: o = 7'b0000110; // 1
4'h2: o = 7'b1011011; // 2
4'h3: o = 7'b1001111; // 3
4'h4: o = 7'b1100110; // 4
4'h5: o = 7'b1101101; // 5
4'h6: o = 7'b1111101; // 6
4'h7: o = 7'b0000111; // 7
4'h8: o = 7'b1111111; // 8
4'h9: o = 7'b1101111; // 9
4'hA: o = 7'b1110111; // A
4'hB: o = 7'b1111100; // b
4'hC: o = 7'b0111001; // C
4'hD: o = 7'b1011110; // d
4'hE: o = 7'b1111001; // E
default: o = 7'b1110001; // F
endcase
end
assign {o6, o5, o4, o3, o2, o1, o0} = o;
endmoduleThe following peripheral and clock configurations are set up using MPLAB Code Configurator (MCC) Melody for the PIC16F13276:
-
Configurations Bits:
- CONFIG1:
- External Oscillator mode selection bits: Oscillator not enabled
- Power-up default value for COSC bits: HFINTOSC (1MHz)
- CONFIG2:
- Brown-out reset enable bits: Brown-out reset disabled
- Brown-out reset enable bits: Brown-out reset disabled
- CONFIG3:
- WDT operating mode: WDT Disabled, SEN is ignored
- WDT operating mode: WDT Disabled, SEN is ignored
- CONFIG1:
-
Clock Control:
- Clock Source: HFINTOSC
- HF Internal Clock: 4_MHz
- Clock Divider: 1
-
CLB1:
- Enable CLB: Enabled
- Clock Selection: HFINTOSC
- Clock Divider: Divide clock source by 1
-
CRC:
- Auto-configured by CLB
-
Pin Grid View:
- CLBPPSOUT0: RA0 (Signal to
adisplay segment) - CLBPPSOUT1: RA1 (Signal to
bdisplay segment) - CLBPPSOUT2: RA2 (Signal to
cdisplay segment) - CLBPPSOUT3: RA3 (Signal to
ddisplay segment) - CLBPPSOUT4: RA4 (Signal to
edisplay segment) - CLBPPSOUT5: RA5 (Signal to
fdisplay segment) - CLBPPSOUT6: RA6 (Signal to
gdisplay segment)
- CLBPPSOUT0: RA0 (Signal to
The demo below presents the incrementing numbers in hexadecimal between 0 and F (hexadecimal values) that are shown on the 7-segment display.
The 330 ohm resistors are needed to limit the current between each LED and I/O pins of the microcontroller.
Note: The demo is at 2x speed.
This example demonstrates the capabilities of the CLB, a CIP that can manipulate the data from the software, while also displaying it in a 7-segment LED view.
This chapter demonstrates how to use the MPLAB X IDE to program a PIC® device with an Example_Project.X. This is applicable to other projects.
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Connect the board to the PC.
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Open the
Example_Project.Xproject in MPLAB X IDE. -
Set the
Example_Project.Xproject as main project.
Right click the project in the Projects tab and click Set as Main Project.
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Clean and build the Example_Project.X project.
Right click the Example_Project.X project and select Clean and Build.
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Select PICxxxxx Curiosity Nano in the Connected Hardware Tool section of the project settings:
Right click the project and click Properties.
Click the arrow under Connected Hardware Tool.
Select PICxxxxx Curiosity Nano (click the SN), click Apply and then OK:
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Program the project to the board.
Right click the project and click Make and Program Device.
