zephyr: rename ACE30 SoC

rename CONFIG_SOC_INTEL_ACE30_PTL -> CONFIG_SOC_INTEL_ACE30 Signed-off-by: Anas Nashif <[email protected]>
nashif · Sep 24, 2024 · 2e56775 · 2e56775
1 parent 0e4c4ef
commit 2e56775
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Showing 3 changed files with 7 additions and 7 deletions.
diff --git a/src/audio/base_fw_intel.c b/src/audio/base_fw_intel.c
@@ -63,7 +63,7 @@ int basefw_vendor_hw_config(uint32_t *data_offset, char *data)
 	tuple = tlv_next(tuple);
 	tlv_value_uint32_set(tuple, IPC4_LP_EBB_COUNT_HW_CFG, PLATFORM_LPSRAM_EBB_COUNT);
 
-#ifdef CONFIG_SOC_INTEL_ACE30_PTL
+#ifdef CONFIG_SOC_INTEL_ACE30
 	tuple = tlv_next(tuple);
 	tlv_value_uint32_set(tuple, IPC4_I2S_CAPS_HW_CFG, I2S_VER_30_PTL);
 #endif

diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt
@@ -238,7 +238,7 @@ if (CONFIG_SOC_SERIES_INTEL_ADSP_ACE)
 			${SOF_PLATFORM_PATH}/lunarlake/lib/clk.c
 		)
 
-	zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_ACE30_PTL
+	zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_ACE30
 			${SOF_PLATFORM_PATH}/pantherlake/lib/clk.c
 		)
 
@@ -268,7 +268,7 @@ if (CONFIG_SOC_SERIES_INTEL_ADSP_ACE)
 		set(PLATFORM "meteorlake")
 	elseif(CONFIG_SOC_INTEL_ACE20_LNL)
 		set(PLATFORM "lunarlake")
-	elseif(CONFIG_SOC_INTEL_ACE30_PTL)
+	elseif(CONFIG_SOC_INTEL_ACE30)
 		set(PLATFORM "pantherlake")
 	endif()
 

diff --git a/zephyr/lib/dma.c b/zephyr/lib/dma.c
@@ -78,12 +78,12 @@ SHARED_DATA struct dma dma[] = {
 	.plat_data = {
 		.dir		= DMA_DIR_DEV_TO_MEM,
 		.caps		= DMA_CAP_HDA,
-#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
+#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
 		.devs		= DMA_DEV_HDA | DMA_DEV_SSP |
 					  DMA_DEV_DMIC | DMA_DEV_ALH,
 #else
 		.devs		= DMA_DEV_HDA,
-#endif /* CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL */
+#endif /* CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 */
 		.channels	= DT_PROP(DT_NODELABEL(hda_link_in), dma_channels),
 		.period_count	= HDA_DMA_BUFFER_PERIOD_COUNT,
 	},
@@ -95,12 +95,12 @@ SHARED_DATA struct dma dma[] = {
 	.plat_data = {
 		.dir		= DMA_DIR_MEM_TO_DEV,
 		.caps		= DMA_CAP_HDA,
-#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
+#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
 		.devs		= DMA_DEV_HDA | DMA_DEV_SSP |
 					  DMA_DEV_DMIC | DMA_DEV_ALH,
 #else
 		.devs		= DMA_DEV_HDA,
-#endif /* CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL */
+#endif /* CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 */
 		.channels	= DT_PROP(DT_NODELABEL(hda_link_out), dma_channels),
 		.period_count	= HDA_DMA_BUFFER_PERIOD_COUNT,
 	},