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[AssignChannels] Prioritize channel assignment for control packets #1106

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merged 3 commits into from
Feb 15, 2025

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Yu-Zhewen
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@Yu-Zhewen Yu-Zhewen commented Feb 14, 2025

Changes in this PR:

  • Previously, channels for data flows were assigned first using the AssignChannels pass, followed by control flow channel assignment with the GenerateControlOverlay pass. This PR reverses the order, ensuring that control flow channels are assigned before data flow channels.
  • Previously, in the runtime ChannelGenerator, packet flow channels were not explicitly marked as assigned (so that they can be reused), while only circuit flow channels were tracked. However, this could result in a packet flow channel later being mistakenly reused by another circuit flow. Now, both circuit and packet flows track their assigned channels and store them separately. This ensures that circuit flow channels remain exclusive, while packet flow channels can be reused but only by other packet flows.

ChannelAssignmentMode mode) {
std::optional<uint8_t> channel;
switch (mode) {
// Select the first available channel for circuit flow.
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I would prefer the docs inside the case statements for readability.

if (!assignedProducerChannels.count(i)) {
lastRetrievedProducerChannel = i;
return i;
// Select the first available channel for packet flow.
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I would prefer the docs inside the the case statements for readability.

i = (lastRetrievedProducerChannel + offset) % numProducerChannels;
} else {
assert(false && "Unsupported ChannelAssignmentMode");
std::optional<uint8_t> getAndAssignProducerDMAChannel(
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I think we create a .cpp file and add the definitions there.

%channel_0 = amdaie.channel(%tile_0_0, 0, port_type = CTRL, direction = S2MM)
%3 = amdaie.logicalobjectfifo.placeholder{%tile_0_0} : !amdaie.logicalobjectfifo<memref<?xi32>>
%4 = amdaie.logicalobjectfifo.placeholder{%tile_0_0} : !amdaie.logicalobjectfifo<memref<?xi32>>
%5 = amdaie.connection(%4 {%channel_0}, %3 {%channel}) {connection_type = #amdaie<connection_type Packet>} : (!amdaie.logicalobjectfifo<memref<?xi32>>, !amdaie.logicalobjectfifo<memref<?xi32>>)
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Could you add a test as well with a pre-existing circuit connection or update this one to include both?

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Added the test at:

func.func @previously_assigned_circuit(%arg0: memref<1x1x8x16xi32, 1>, %arg1: memref<8x16xi32>) {

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LGTM

@jtuyls jtuyls merged commit 54b89c2 into main Feb 15, 2025
6 of 7 checks passed
@jtuyls jtuyls deleted the zhewen_channels branch February 15, 2025 11:22
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2 participants