nRF54L15: Add initial TF-M support

boards/arm/nrf54l15pdk_nrf54l15/Kconfig.board

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+# Copyright (c) 2022 Nordic Semiconductor ASA
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+if SOC_NRF54L15_ENGA_CPUAPP
+
+config BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS
+	bool "nRF54L15 DK nRF54L15 Application MCU non-secure"
+
+endif # SOC_NRF54L15_CPUAPP

boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig

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+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+if BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS
+
+config BOARD
+	default "nrf54l15pdk_nrf54l15_cpuapp"
+
+# By default, if we build for a Non-Secure version of the board,
+# enable building with TF-M as the Secure Execution Environment.
+config BUILD_WITH_TFM
+	default y if BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS
+
+# By default, if we build with TF-M, instruct build system to
+# flash the combined TF-M (Secure) & Zephyr (Non Secure) image
+config TFM_FLASH_MERGED_BINARY
+	bool
+	default y
+	depends on BUILD_WITH_TFM
+
+# TODO: Remove the options bellow when (NCSDK-25023) is done
+config NRF_SPU_FLASH_REGION_SIZE
+	hex
+	default 0x4000
+	# This option does not apply to 54, but we pretend the HW has this limitation
+	# for now for easier porting. NCSDK-25023
+	help
+	  FLASH region size for the NRF_SPU peripheral. For nrf54 the
+	  region size is configurable per-region so this option does
+	  not apply.
+
+config NRF_SPU_FLASH_REGION_ALIGNMENT
+	hex
+	default 0x4000
+	# This option does not apply to 54, but we pretend the HW has this limitation
+	# for now for easier porting. NCSDK-25023
+	help
+	  FLASH region size for the NRF_SPU peripheral. For nrf54 the
+	  region size is configurable per-region so this option does
+	  not apply.
+
+config NRF_SPU_RAM_REGION_SIZE
+	hex
+	default 0x2000
+	# This HW limitation does not apply to 54, but we pretend
+	# it does for now for easier porting. NCSDK-25023
+	help
+	  RAM region size for the NRF_SPU peripheral. For nrf54 the
+	  region size is configurable per-region so this option does
+	  not apply.
+
+
+config NRF_SPU_RAM_REGION_ALIGNMENT
+	hex
+	default 0x1000
+	help
+	  RAM regions must be aligned to this value due to SPU HW
+	  limitations.
+
+endif #BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS

boards/arm/nrf54l15pdk_nrf54l15/board.cmake

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+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+if(CONFIG_BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS)
+  board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
+endif()
+
+if(BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS)
+  set(TFM_PUBLIC_KEY_FORMAT "full")
+endif()
+
+if(CONFIG_TFM_FLASH_MERGED_BINARY)
+  set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.yaml

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+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+identifier: nrf54l15pdk_nrf54l15_cpuapp_ns
+name: nRF54l15-PDK-nRF54l15-Application-Non-Secure
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - xtools
+  - zephyr
+ram: 256
+flash: 1524
+supported:
+  - adc
+  - gpio
+  - i2c
+  - spi
+  - counter
+  - watchdog
+  - adc
+  - i2s

boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_ns-pinctrl.dtsi

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+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+&pinctrl {
+	uart20_default: uart20_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RX, 1, 5)>;
+		};
+	};
+
+	uart20_sleep: uart20_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RX, 1, 5)>;
+			low-power-enable;
+		};
+	};
+
+	uart30_default: uart30_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RX, 0, 1)>;
+		};
+	};
+
+	uart30_sleep: uart30_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RX, 0, 1)>;
+			low-power-enable;
+		};
+	};
+
+};

boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_ns.dts

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+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/dts-v1/;
+#include <nordic/nrf54l15_cpuapp_ns.dtsi>
+#include "nrf54l15pdk_nrf54l15_cpuapp_ns-pinctrl.dtsi"
+
+/ {
+	chosen {
+		zephyr,console = &uart20;
+		/* TODO: NCSDK-24862: We don't support configuring RRAM and SRAM
+		 * regions in the DTS file yet. The partition manager configures
+		 * these regions now.
+		 */
+		zephyr,shell-uart = &uart20;
+		zephyr,flash = &rram0;
+		zephyr,sram = &sram0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led0: led_0 {
+			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 0";
+		};
+		led1: led_1 {
+			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 1";
+		};
+		led2: led_2 {
+			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 2";
+		};
+		led3: led_3 {
+			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 3";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+		button0: button_0 {
+			gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 0";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+		button1: button_1 {
+			gpios = <&gpio1 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 1";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+		button2: button_2 {
+			gpios = <&gpio2 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 2";
+			zephyr,code = <INPUT_KEY_2>;
+		};
+		button3: button_3 {
+			gpios = <&gpio2 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 3";
+			zephyr,code = <INPUT_KEY_3>;
+		};
+	};
+
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		led2 = &led2;
+		led3 = &led3;
+		sw0 = &button0;
+		sw1 = &button1;
+		sw2 = &button2;
+		sw3 = &button3;
+	};
+};
+
+&uart20 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart20_default>;
+	pinctrl-1 = <&uart20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&uart30 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&grtc {
+	status = "okay";
+};

boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_ns_defconfig

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+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+CONFIG_SOC_SERIES_NRF54LX=y
+CONFIG_SOC_NRF54L15_ENGA_CPUAPP=y
+CONFIG_BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+
+# Enable TrustZone-M
+CONFIG_ARM_TRUSTZONE_M=y
+
+# This Board implies building Non-Secure firmware
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+
+# Don't enable the cache in the non-secure image as it is a
+# secure-only peripheral on 54l
+CONFIG_CACHE_MANAGEMENT=n
+CONFIG_EXTERNAL_CACHE=n
+
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# NCSDK-22600: Protected storage depends on BUILTIN_KEYS
+CONFIG_TFM_PARTITION_PROTECTED_STORAGE=n
+
+# NCSDK-22600: Built-in keys are not supported yet.
+CONFIG_TFM_CRYPTO_BUILTIN_KEYS=n
+
+# Start SYSCOUNTER on driver init
+CONFIG_NRF_GRTC_START_SYSCOUNTER=y

dts/arm/nordic/nrf54l15_cpuapp_ns.dtsi

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+ /*
+  * Copyright (c) 2024 Nordic Semiconductor ASA
+  *
+  * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+  */
+
+#include <arm/armv8-m.dtsi>
+#include <nordic/nrf_common.dtsi>
+#include <nordic/nrf54l_common.dtsi>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu: cpu@0 {
+			clock-frequency = <DT_FREQ_M(128)>;
+			device_type = "cpu";
+			compatible = "arm,cortex-m33f";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			itm: itm@e0000000 {
+				compatible = "arm,armv8m-itm";
+				reg = <0xe0000000 0x1000>;
+				swo-ref-frequency = <DT_FREQ_M(128)>;
+			};
+		};
+	};
+
+	clocks {
+		lfxo: lfxo {
+			compatible = "nordic,nrf-lfxo";
+			#clock-cells = <0>;
+			clock-frequency = <32768>;
+		};
+
+		hfxo: hfxo {
+			compatible = "nordic,nrf-hfxo";
+			#clock-cells = <0>;
+			clock-frequency = <DT_FREQ_M(32)>;
+		};
+	};
+
+	soc {
+		ficr: ficr@ffc000 {
+			compatible = "nordic,nrf-ficr";
+			reg = <0xffc000 0x1000>;
+			#nordic,ficr-cells = <1>;
+		};
+
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(256)>;
+		};
+
+		peripheral@40000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x40000000 0x10000000>;
+
+			/* Common nRF54L15 peripheral description */
+			#include "nrf54l15_cpuapp_peripherals_ns.dtsi"
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
+
+&rram_controller {
+	rram0: rram@0 {
+		/*
+		 * "1524 KB non-volatile memory (RRAM) and 256 KB RAM"
+		 *    -- Product Specification
+		 * NB: 1524 = 1.5 * 1024 - 12
+		 */
+		reg = <0x0 DT_SIZE_K(1524)>;
+	};
+};
+
+/* Disable by default to use GRTC */
+&systick {
+	status = "disabled";
+};