-
Notifications
You must be signed in to change notification settings - Fork 5.8k
8355667: RISC-V: Add backend implementation for unsigned vector Min / Max operations #24909
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Conversation
👋 Welcome back fyang! A progress list of the required criteria for merging this PR into |
@RealFYang This change now passes all automated pre-integration checks. ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details. After integration, the commit message for the final commit will be:
You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed. At the time when this comment was updated there had been no new commits pushed to the ➡️ To integrate this PR with the above commit message to the |
@RealFYang The following label will be automatically applied to this pull request:
When this pull request is ready to be reviewed, an "RFR" email will be sent to the corresponding mailing list. If you would like to change these labels, use the /label pull request command. |
Webrevs
|
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
LGTM.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Looks good.
Just one minor question, should we add an assert like below for these instructs? Seems not, but I'm not quite sure.
assert(Matcher::vector_element_basic_type(n) != T_FLOAT &&
Matcher::vector_element_basic_type(n) != T_DOUBLE);
Good suggestion! I have added following assertion for these instructions just like other CPU ports.
|
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Thanks for updating, still good!
Thanks for the review! Let's |
@RealFYang Pushed as commit 2ed7ad4. 💡 You may see a message that your pull request was closed with unmerged commits. This can be safely ignored. |
Hi, please review this change.
https://bugs.openjdk.org/browse/JDK-8338021 proposed new vector operators including Unsigned Vector Min / Max.
This intrinsify Unsigned Vector Min / Max operations with RVV extension for RISC-V backend to improve performance.
This also enables some extra IR tests in file
test/hotspot/jtreg/compiler/vectorapi/VectorCommutativeOperSharingTest.java
.Testing:
JMH tested on BPI-F3 SBC (256-bit VLEN) for reference:
Before:
After:
Progress
Issue
Reviewers
Reviewing
Using
git
Checkout this PR locally:
$ git fetch https://git.openjdk.org/jdk.git pull/24909/head:pull/24909
$ git checkout pull/24909
Update a local copy of the PR:
$ git checkout pull/24909
$ git pull https://git.openjdk.org/jdk.git pull/24909/head
Using Skara CLI tools
Checkout this PR locally:
$ git pr checkout 24909
View PR using the GUI difftool:
$ git pr show -t 24909
Using diff file
Download this PR as a diff file:
https://git.openjdk.org/jdk/pull/24909.diff
Using Webrev
Link to Webrev Comment