Merge commit 'b1e1ec64f13dda135b3042c56099bb39eed4e660'

Author: wallento

osd-hardware/blocks/buffer/verilog/dii_buffer.sv

@@ -1,93 +1,94 @@
 
+import dii_package::dii_flit;
+
 module dii_buffer
-  #(parameter WIDTH=16,
-    parameter SIZE=4,
-    parameter FULLPACKET=0)
+  #(
+    parameter BUF_SIZE = 4,                     // length of the buffer
+    parameter FULLPACKET = 0
+    )
    (
-    input clk,
-    input rst,
-
-    dii_channel.slave in,
-    dii_channel.master out
-    );
-
-   // Signals for fifo
-   logic [WIDTH-1:0] fifo_data [0:SIZE-1]; //actual fifo
-   logic [SIZE-1:0]  fifo_first; //actual fifo
-   logic [SIZE-1:0]  fifo_last; //actual fifo
-   logic [WIDTH-1:0] nxt_fifo_data [0:SIZE-1];
-   logic [SIZE-1:0]  nxt_fifo_first;
-   logic [SIZE-1:0]  nxt_fifo_last;
-   
-   reg [SIZE:0]      fifo_write_ptr;
-   
-   logic             pop;
-   logic             push;
-   logic             full_packet;
-
-   logic [SIZE-1:0]   valid;
-   always_comb @(*) begin : valid_comb
-      integer i;
-      // Set first element
-      valid[SIZE-1] = fifo_write_ptr[SIZE];
-      for (i = SIZE - 2; i >= 0; i = i - 1) begin
-         valid[i] = fifo_write_ptr[i+1] | valid[i+1];
-      end
-   end
+    input                               clk, rst,
+    output logic [$clog2(BUF_SIZE):0]   packet_size,
+
+    input  dii_flit                     flit_in,
+    output                              flit_in_ready,
+    output dii_flit                     flit_out,
+    input                               flit_out_ready
+     );
 
-   assign full_packet = |(fifo_last & valid); 
 
-   assign pop = out.valid & out.ready;
-   assign push = in.valid & in.ready;
+   localparam ID_W = $clog2(BUF_SIZE); // the width of the index
 
-   assign out.data = fifo_data[0][WIDTH-1:0];
-   assign out.first = fifo_data[0][WIDTH+1];
-   assign out.last = fifo_data[0][WIDTH];   
-   assign out.valid = !FULLPACKET ? !fifo_write_ptr[0] : full_packet;
+   // internal shift register
+   dii_flit [BUF_SIZE-1:0]   data;
+   reg [ID_W:0]              rp; // read pointer
+   logic                     reg_out_valid;  // local output valid
+   logic                     flit_in_fire, flit_out_fire;
 
-   assign in.ready = !fifo_write_ptr[SIZE];
+   assign flit_in_ready = (rp != BUF_SIZE - 1) || !reg_out_valid;
+   assign flit_in_fire = flit_in.valid && flit_in_ready;
+   assign flit_out_fire = flit_out.valid && flit_out_ready;
 
-   always @(posedge clk) begin
-      if (rst) begin
-         fifo_write_ptr <= {{SIZE{1'b0}},1'b1};
-      end else if (push & !pop) begin
-         fifo_write_ptr <= fifo_write_ptr << 1;
-      end else if (!push & pop) begin
-         fifo_write_ptr <= fifo_write_ptr >> 1;
-      end
-   end
-
-   always @(*) begin : shift_register_comb
-      integer i;
-      for (i=0;i<SIZE;i=i+1) begin
-         if (pop) begin
-            if (push & fifo_write_ptr[i+1]) begin
-               nxt_fifo_data[i] = in.data;
-               nxt_fifo_first[i] = in.first;
-               nxt_fifo_last[i] = in.last;
-            end else if (i<SIZE-1) begin
-               nxt_fifo_data[i] = fifo_data[i+1];
-            end else begin
-               nxt_fifo_data[i] = fifo_data[i];
-            end
-         end else if (push & fifo_write_ptr[i]) begin
-            nxt_fifo_data[i] = in.data;
-            nxt_fifo_first[i] = in.first;
-            nxt_fifo_last[i] = in.last;
-         end else begin
-            nxt_fifo_data[i] = fifo_data[i];
+   always_ff @(posedge clk)
+     if(rst)
+       reg_out_valid <= 0;
+     else if(flit_in.valid)
+       reg_out_valid <= 1;
+     else if(flit_out_ready && rp == 0)
+       reg_out_valid <= 0;
+
+   always_ff @(posedge clk)
+     if(rst)
+       rp <= 0;
+     else if(flit_in_fire && !flit_out_fire && reg_out_valid)
+       rp <= rp + 1;
+     else if(flit_out_fire && !flit_in_fire && rp != 0)
+       rp <= rp - 1;
+
+   always @(posedge clk)
+     if(flit_in_fire)
+       data <= {data, flit_in};
+
+   generate                     // SRL does not allow parallel read
+      if(FULLPACKET != 0) begin
+         logic [BUF_SIZE-1:0] data_last_buf;
+
+         always @(posedge clk)
+           if(rst)
+             data_last_buf = 0;
+           else begin
+              if(flit_out_fire)
+                data_last_buf[rp] = 1'b0;
+              if(flit_in_fire)
+                data_last_buf = {data_last_buf, flit_in.last && flit_in.valid};
+           end
+
+         // extra logic to get the packet size in a stable manner
+         logic [BUF_SIZE:0] data_last_shifted;
+         assign data_last_shifted = {1'b0,data_last_buf} << BUF_SIZE - rp;
+
+         function logic [ID_W:0] find_first_one(input logic [BUF_SIZE:0] data);
+            automatic int i;
+            for(i=BUF_SIZE; i>0; i--)
+              if(data[i]) return i;
+            return BUF_SIZE;
+         endfunction // size_count
+
+         assign packet_size = BUF_SIZE + 1 - find_first_one(data_last_shifted);
+         always_comb begin
+            flit_out.valid = |data_last_buf;
+            flit_out.last = data[rp].last;
+            flit_out.data = data[rp].data;
+         end
+      end else begin // if (FULLPACKET)
+         assign packet_size = 0;
+         always_comb begin
+            flit_out.valid = reg_out_valid;
+            flit_out.last = data[rp].last;
+            flit_out.data = data[rp].data;
          end
       end
-   end
-
-   always @(posedge clk) begin : shift_register_seq
-      integer i;
-      for (i=0;i<SIZE;i=i+1) begin
-         fifo_data[i] <= nxt_fifo_data[i];
-         fifo_first[i] <= nxt_fifo_first[i];
-         fifo_last[i] <= nxt_fifo_last[i];
-      end
-   end
-   
+   endgenerate
+
 endmodule // dii_buffer