Merge commit '18aad0db798716df2b569a41a6cf55b8360eb595'

Author: wallento

glip/src/backend_tcp/logic/dpi/glip_tcp_toplevel.sv

@@ -22,6 +22,7 @@
  *
  * Author(s):
  *   Stefan Wallentowitz <[email protected]>
+ *   Wei Song <[email protected]>
  */
 
 module glip_tcp_toplevel

glip/src/common/logic/scaler/verilog/glip_downscale.v

@@ -41,17 +41,17 @@ module glip_downscale
     output                 out_valid,
     input                  out_ready);
 
-   /* 0 when passthrough and 1 when emitting upper part */
+   /* 0 when passthrough and 1 when emitting lower part */
    reg                     scale;
-   /* Store upper part for emitting in second transfer */
-   reg [OUT_SIZE-1:0]      upper;
+   /* Store lower part for emitting in second transfer */
+   reg [OUT_SIZE-1:0]      lower;
 
    /* Ready during passthrough */
    assign in_ready = !scale & out_ready;
    /* Valid during passthrough or second transfer */
-   assign out_valid = scale ? 1 : in_valid;
-   /* Passthrough in first and stored upper in second transfer */
-   assign out_data = !scale ? in_data[OUT_SIZE-1:0] : upper; 
+   assign out_valid = scale | in_valid;
+   /* Passthrough in first and stored lower in second transfer */
+   assign out_data = scale ? lower : in_data[OUT_SIZE*2-1:OUT_SIZE];
 
    always @(posedge clk) begin
       if (rst) begin
@@ -65,7 +65,7 @@ module glip_downscale
 
    always @(posedge clk) begin
       if (in_valid & in_ready) begin
-         upper <= in_data[OUT_SIZE*2-1:OUT_SIZE];
+         lower <= in_data[OUT_SIZE-1:0];
       end
    end
 

glip/src/common/logic/scaler/verilog/glip_upscale.v

@@ -43,15 +43,15 @@ module glip_upscale
 
    /* 0 while storing the first part and 1 when emitting */
    reg                      scale;
-   /* Store lower part for second cycle */
-   reg [IN_SIZE-1:0]        lower;
+   /* Store upper part for second cycle */
+   reg [IN_SIZE-1:0]        upper;
 
    /* Ready to store on first part and then passthrough in second */
    assign in_ready = !scale | out_ready;
    /* Valid in second part */
    assign out_valid = scale & in_valid;
    /* Assemble data */
-   assign out_data = { in_data, lower };
+   assign out_data = { upper, in_data };
 
    always @(posedge clk) begin
       if (rst) begin
@@ -65,7 +65,7 @@ module glip_upscale
 
    always @(posedge clk) begin
       if (in_valid & in_ready) begin
-         lower <= in_data;
+         upper <= in_data;
       end
    end
 endmodule // glip_upscale