Try building the trace pipeline for icebreaker.

icebreaker_builder.py

@@ -0,0 +1,113 @@
+#!/usr/bin/env python3
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litex_boards.platforms import icebreaker
+
+from litex.build.generic_platform import *
+
+from litex.soc.cores.clock import iCE40PLL
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+
+from orbtrace.trace import TraceCore
+
+# CRG ----------------------------------------------------------------------------------------------
+
+class _CRG(Module):
+    def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
+        self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_por = ClockDomain()
+
+        self.clock_domains.cd_swo = ClockDomain()
+        self.clock_domains.cd_swo2x = ClockDomain()
+
+        # # #
+
+        # Clk/Rst
+        clk12 = platform.request("clk12")
+        rst_n = platform.request("user_btn_n")
+
+        # Power On Reset
+        por_count = Signal(16, reset=2**16-1)
+        por_done  = Signal()
+        self.comb += self.cd_por.clk.eq(ClockSignal())
+        self.comb += por_done.eq(por_count == 0)
+        self.sync.por += If(~por_done, por_count.eq(por_count - 1))
+
+        # PLL
+        self.submodules.pll = pll = iCE40PLL(primitive="SB_PLL40_PAD")
+        self.comb += pll.reset.eq(~rst_n) # FIXME: Add proper iCE40PLL reset support and add back | self.rst.
+        pll.register_clkin(clk12, 12e6)
+        pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
+        self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
+        platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    def __init__(self, sys_clk_freq=int(24e6), **kwargs):
+        platform = icebreaker.Platform()
+
+        platform.add_extension([
+            ('trace', 0,
+                Subsignal('clk', Pins('PMOD1A:1')),
+                Subsignal('data', Pins('PMOD1A:2 PMOD1A:3 PMOD1A:4 PMOD1A:5')),
+            ),
+        ])
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, sys_clk_freq,
+            ident = "LiteX SoC on iCEBreaker",
+            **kwargs)
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
+        self.submodules.trace = TraceCore(platform)
+
+        self.comb += self.trace.input_format.eq(0x03) # Hardwire for 4-bit parallel trace.
+
+        self.comb += self.trace.source.connect(self.uart.sink) 
+
+
+# Flash --------------------------------------------------------------------------------------------
+
+def flash(build_dir, build_name, bios_flash_offset):
+    from litex.build.lattice.programmer import IceStormProgrammer
+    prog = IceStormProgrammer()
+    prog.flash(bios_flash_offset, f"{build_dir}/software/bios/bios.bin")
+    prog.flash(0x00000000,        f"{build_dir}/gateware/{build_name}.bin")
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    from litex.soc.integration.soc import LiteXSoCArgumentParser
+    parser = LiteXSoCArgumentParser(description="LiteX SoC on iCEBreaker")
+    target_group = parser.add_argument_group(title="Target options")
+    target_group.add_argument("--build",               action="store_true", help="Build bitstream.")
+    target_group.add_argument("--load",                action="store_true", help="Load bitstream.")
+    target_group.add_argument("--flash",               action="store_true", help="Flash Bitstream and BIOS.")
+    target_group.add_argument("--sys-clk-freq",        default=24e6,        help="System clock frequency.")
+    builder_args(parser)
+    soc_core_args(parser)
+    args = parser.parse_args()
+
+    soc = BaseSoC(
+        sys_clk_freq        = int(float(args.sys_clk_freq)),
+        **soc_core_argdict(args)
+    )
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build(run=args.build)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(builder.get_bitstream_filename(mode="sram", ext=".bin")) # FIXME
+
+    if args.flash:
+        flash(builder.output_dir, soc.build_name, args.bios_flash_offset)
+
+if __name__ == "__main__":
+    main()

pyproject.toml

@@ -24,6 +24,7 @@ dynamic = ["version"]
 
 [project.scripts]
 orbtrace_builder = "orbtrace_builder:main"
+icebreaker_builder = "icebreaker_builder:main"
 
 [build-system]
 requires = ["pdm-backend"]