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Added simple UART logger
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‎axi4l_logger.sv

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//------------------------------------------------------------------------------
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// axi4l_logger.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, [email protected]
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// AXI4-Lite logger
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// Sniffs all AXI transactions and stores address and data to fifo
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//
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// - optimized for `AXI_ADDR_WIDTH = 32 and `AXI_DATA_WIDTH = 32
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//
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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axi4l_logger AL (
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.clk_axi( ),
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.anrst_axi( ),
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// axi interface here
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.clk( ),
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.empty( )
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.r_req( ),
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.r_rnw( ),
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.r_addr( ),
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.r_data( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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module axi4l_logger #( parameter
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bit [`AXI_ADDR_WIDTH-1:0] REG_ADDRESS_FROM = '0, // register address
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bit [`AXI_ADDR_WIDTH-1:0] REG_ADDRESS_TO = '1 // space to log
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)(
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input clk_axi, // axi clock
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input anrst_axi, // axi async reset (inversed)
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input [`AXI_ADDR_WIDTH-1:0] s_axi_araddr, // axil
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input [1:0] s_axi_arburst,
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input [3:0] s_axi_arcache,
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input [`AXI_LEN_WIDTH-1:0] s_axi_arlen,
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input [0:0] s_axi_arlock,
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input [2:0] s_axi_arprot, // axil // NU here
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input [3:0] s_axi_arqos,
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input s_axi_arready, // axil
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input [3:0] s_axi_arregion,
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input [`AXI_SIZE_WIDTH-1:0] s_axi_arsize,
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input s_axi_arvalid, // axil
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input [`AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // axil
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input [1:0] s_axi_awburst,
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input [3:0] s_axi_awcache,
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input [`AXI_LEN_WIDTH-1:0] s_axi_awlen,
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input [0:0] s_axi_awlock,
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input [2:0] s_axi_awprot, // axil // NU here
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input [3:0] s_axi_awqos,
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input s_axi_awready, // axil
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input [3:0] s_axi_awregion,
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input [`AXI_SIZE_WIDTH-1:0] s_axi_awsize,
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input s_axi_awvalid, // axil
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input s_axi_bready, // axil
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input [1:0] s_axi_bresp, // axil
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input s_axi_bvalid, // axil
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input [`AXI_DATA_WIDTH-1:0] s_axi_rdata, // axil
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input s_axi_rlast,
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input s_axi_rready, // axil
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input [1:0] s_axi_rresp, // axil
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input s_axi_rvalid, // axil
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input [`AXI_DATA_WIDTH-1:0] s_axi_wdata, // axil
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input s_axi_wlast,
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input s_axi_wready, // axil
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input [`AXI_DATA_BYTES-1:0] s_axi_wstrb, // axil
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input s_axi_wvalid, // axil
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// fifo output interface
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input clk,
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output empty,
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input r_req,
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output r_rnw,
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output [`AXI_ADDR_WIDTH-1:0] r_addr,
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output [`AXI_DATA_WIDTH-1:0] r_data
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);
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logic aw_w_req; // axi addr write request
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logic ar_w_req; // axi addr read request
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logic aw_w_req_d1;
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logic ar_w_req_d1;
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always_ff @( posedge clk_axi or negedge anrst_axi ) begin
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if( ~anrst_axi ) begin
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aw_w_req_d1 <= 1'b0;
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ar_w_req_d1 <= 1'b0;
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end else begin
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aw_w_req_d1 <= aw_w_req;
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ar_w_req_d1 <= ar_w_req;
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end
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end
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// WRITE =======================================================================
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logic aw_en = 1'b1;
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always_ff @( posedge clk_axi or negedge anrst_axi ) begin
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if ( ~anrst_axi ) begin
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aw_en <= 1'b1;
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end else begin
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if (~s_axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) begin
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aw_en <= 1'b0;
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end else if (s_axi_bready && s_axi_bvalid) begin
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aw_en <= 1'b1;
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end
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end
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end
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logic [`AXI_DATA_WIDTH-1:0] s_axi_awaddr_buf = '0;
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always_ff @( posedge clk_axi or negedge anrst_axi ) begin
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if ( ~anrst_axi ) begin
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s_axi_awaddr_buf[`AXI_DATA_WIDTH-1:0] <= '0;
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end else begin
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if (~s_axi_awready && s_axi_awvalid && s_axi_wvalid && aw_en) begin
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s_axi_awaddr_buf[`AXI_DATA_WIDTH-1:0] <= s_axi_awaddr[`AXI_DATA_WIDTH-1:0];
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end
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end
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end
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always_comb begin
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aw_w_req = s_axi_wready && s_axi_wvalid && s_axi_awready && s_axi_awvalid &&
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(s_axi_awaddr_buf[`AXI_ADDR_WIDTH-1:0] >= REG_ADDRESS_FROM[`AXI_ADDR_WIDTH-1:0]) &&
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(s_axi_awaddr_buf[`AXI_ADDR_WIDTH-1:0] <= REG_ADDRESS_TO[`AXI_ADDR_WIDTH-1:0]);
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end
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// READ ========================================================================
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logic [`AXI_ADDR_WIDTH-1:0] s_axi_araddr_buf = '0;
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always_ff @( posedge clk_axi or negedge anrst_axi ) begin
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if ( ~anrst_axi ) begin
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s_axi_araddr_buf[`AXI_ADDR_WIDTH-1:0] <= '0;
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end else begin
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if (~s_axi_arready && s_axi_arvalid) begin
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s_axi_araddr_buf[`AXI_ADDR_WIDTH-1:0] <= s_axi_araddr[`AXI_ADDR_WIDTH-1:0];
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end
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end
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end
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always_comb begin
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ar_w_req = s_axi_arready && s_axi_arvalid && ~s_axi_rvalid &&
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(s_axi_araddr_buf[`AXI_ADDR_WIDTH-1:0] >= REG_ADDRESS_FROM[`AXI_ADDR_WIDTH-1:0]) &&
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(s_axi_araddr_buf[`AXI_ADDR_WIDTH-1:0] <= REG_ADDRESS_TO[`AXI_ADDR_WIDTH-1:0]);
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end
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// FIFO ========================================================================
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// fifo inputs
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logic [31:0] w_addr_f;
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logic [31:0] w_data_f;
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logic [31:0] w_rnwr_f;
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always_comb begin
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if( aw_w_req_d1 ) begin
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w_addr_f[31:0] = s_axi_awaddr_buf[31:0];
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w_data_f[31:0] = s_axi_wdata[31:0];
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w_rnwr_f[31:0] = '0;
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end else if( ar_w_req_d1 ) begin
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w_addr_f[31:0] = s_axi_araddr_buf[31:0];
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w_data_f[31:0] = s_axi_rdata[31:0];
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w_rnwr_f[31:0] = 32'b1;
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end else begin
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w_addr_f[31:0] = '0;
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w_data_f[31:0] = '0;
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w_rnwr_f[31:0] = '0;
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end
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end
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// fifo outputs
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logic [31:0] r_addr_f;
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logic [31:0] r_data_f;
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logic [31:0] r_rnwr_f;
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FIFO18E1 #(
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.ALMOST_EMPTY_OFFSET ( 13'h0006 ), // min. value is 6 for FWFT mode, Sets the almost empty threshold
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.ALMOST_FULL_OFFSET ( 13'h0005 ), // min. value is 4, Sets almost full threshold
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.DATA_WIDTH ( 36 ), // Sets data width to 4-36
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.DO_REG ( 1 ), // Enable output register ( 1-0 ) Must be 1 if EN_SYN = FALSE
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.EN_SYN ( "FALSE" ), // Specifies FIFO as dual-clock ( FALSE ) or Synchronous ( TRUE )
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.FIFO_MODE ( "FIFO18_36" ), // Sets mode to FIFO18 or FIFO18_36
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.FIRST_WORD_FALL_THROUGH ( "TRUE" ), // Sets the FIFO FWFT to FALSE, TRUE
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.INIT ( 36'h000000000 ), // Initial values on output port
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.SIM_DEVICE ( "7SERIES" ), // Must be set to "7SERIES" for simulation behavior
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.SRVAL ( 36'h000000000 ) // Set/Reset value for output port
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) addr_fifo_b (
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.RST ( ~anrst_axi ), // 1-bit input: Asynchronous Reset
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.RSTREG ( 1'b0 ), // 1-bit input: Output register set/reset
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.WRCLK ( clk_axi ), // 1-bit input: Write clock
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.WREN ( aw_w_req_d1 || ar_w_req_d1 ), // 1-bit input: Write enable
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.DI ( w_addr_f[31:0] ), // 32-bit input: Data input
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.DIP ( 4'b0 ), // 4-bit input: Parity input
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.FULL ( ), // 1-bit output: Full flag
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.ALMOSTFULL ( ), // 1-bit output: Almost full flag
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.WRCOUNT ( ), // 12-bit output: Write count
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.WRERR ( ), // 1-bit output: Write error
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.RDCLK ( clk ), // 1-bit input: Read clock
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.REGCE ( 1'b1 ), // 1-bit input: Clock enable
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.RDEN ( r_req ), // 1-bit input: Read enable
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.DO ( r_addr_f[31:0] ), // 32-bit output: Data output
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.DOP ( ), // 4-bit output: Parity data output
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.EMPTY ( empty ), // 1-bit output: Empty flag
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.ALMOSTEMPTY ( ), // 1-bit output: Almost empty flag
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.RDCOUNT ( ), // 12-bit output: Read count
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.RDERR ( ) // 1-bit output: Read error
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);
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FIFO18E1 #(
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.ALMOST_EMPTY_OFFSET ( 13'h0006 ), // min. value is 6 for FWFT mode, Sets the almost empty threshold
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.ALMOST_FULL_OFFSET ( 13'h0005 ), // min. value is 4, Sets almost full threshold
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.DATA_WIDTH ( 36 ), // Sets data width to 4-36
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.DO_REG ( 1 ), // Enable output register ( 1-0 ) Must be 1 if EN_SYN = FALSE
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.EN_SYN ( "FALSE" ), // Specifies FIFO as dual-clock ( FALSE ) or Synchronous ( TRUE )
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.FIFO_MODE ( "FIFO18_36" ), // Sets mode to FIFO18 or FIFO18_36
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.FIRST_WORD_FALL_THROUGH ( "TRUE" ), // Sets the FIFO FWFT to FALSE, TRUE
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.INIT ( 36'h000000000 ), // Initial values on output port
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.SIM_DEVICE ( "7SERIES" ), // Must be set to "7SERIES" for simulation behavior
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.SRVAL ( 36'h000000000 ) // Set/Reset value for output port
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) data_fifo_b (
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.RST ( ~anrst_axi ), // 1-bit input: Asynchronous Reset
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.RSTREG ( 1'b0 ), // 1-bit input: Output register set/reset
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.WRCLK ( clk_axi ), // 1-bit input: Write clock
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.WREN ( aw_w_req_d1 || ar_w_req_d1 ), // 1-bit input: Write enable
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.DI ( w_data_f[31:0] ), // 32-bit input: Data input
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.DIP ( 4'b0 ), // 4-bit input: Parity input
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.FULL ( ), // 1-bit output: Full flag
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.ALMOSTFULL ( ), // 1-bit output: Almost full flag
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.WRCOUNT ( ), // 12-bit output: Write count
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.WRERR ( ), // 1-bit output: Write error
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.RDCLK ( clk ), // 1-bit input: Read clock
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.REGCE ( 1'b1 ), // 1-bit input: Clock enable
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.RDEN ( r_req ), // 1-bit input: Read enable
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.DO ( r_data_f[31:0] ), // 32-bit output: Data output
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.DOP ( ), // 4-bit output: Parity data output
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.EMPTY ( ), // 1-bit output: Empty flag
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.ALMOSTEMPTY ( ), // 1-bit output: Almost empty flag
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.RDCOUNT ( ), // 12-bit output: Read count
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.RDERR ( ) // 1-bit output: Read error
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);
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FIFO18E1 #(
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.ALMOST_EMPTY_OFFSET ( 13'h0006 ), // min. value is 6 for FWFT mode, Sets the almost empty threshold
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.ALMOST_FULL_OFFSET ( 13'h0005 ), // min. value is 4, Sets almost full threshold
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.DATA_WIDTH ( 36 ), // Sets data width to 4-36
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.DO_REG ( 1 ), // Enable output register ( 1-0 ) Must be 1 if EN_SYN = FALSE
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.EN_SYN ( "FALSE" ), // Specifies FIFO as dual-clock ( FALSE ) or Synchronous ( TRUE )
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.FIFO_MODE ( "FIFO18_36" ), // Sets mode to FIFO18 or FIFO18_36
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.FIRST_WORD_FALL_THROUGH ( "TRUE" ), // Sets the FIFO FWFT to FALSE, TRUE
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.INIT ( 36'h000000000 ), // Initial values on output port
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.SIM_DEVICE ( "7SERIES" ), // Must be set to "7SERIES" for simulation behavior
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.SRVAL ( 36'h000000000 ) // Set/Reset value for output port
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) rnmr_fifo_b (
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.RST ( ~anrst_axi ), // 1-bit input: Asynchronous Reset
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.RSTREG ( 1'b0 ), // 1-bit input: Output register set/reset
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.WRCLK ( clk_axi ), // 1-bit input: Write clock
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.WREN ( aw_w_req_d1 || ar_w_req_d1 ), // 1-bit input: Write enable
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.DI ( w_rnwr_f[31:0] ), // 32-bit input: Data input
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.DIP ( 4'b0 ), // 4-bit input: Parity input
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.FULL ( ), // 1-bit output: Full flag
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.ALMOSTFULL ( ), // 1-bit output: Almost full flag
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.WRCOUNT ( ), // 12-bit output: Write count
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.WRERR ( ), // 1-bit output: Write error
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.RDCLK ( clk ), // 1-bit input: Read clock
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.REGCE ( 1'b1 ), // 1-bit input: Clock enable
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.RDEN ( r_req ), // 1-bit input: Read enable
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.DO ( r_rnwr_f[31:0] ), // 32-bit output: Data output
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.DOP ( ), // 4-bit output: Parity data output
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.EMPTY ( ), // 1-bit output: Empty flag
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.ALMOSTEMPTY ( ), // 1-bit output: Almost empty flag
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.RDCOUNT ( ), // 12-bit output: Read count
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.RDERR ( ) // 1-bit output: Read error
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);
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assign r_rnw = r_rnwr_f[0];
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assign r_addr[31:0] = r_addr_f[31:0];
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assign r_data[31:0] = r_data_f[31:0];
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endmodule
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