[Types] Support wiring Bit and Bits[1]#1070
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Two implementation issues: 1. Should we support wiring T to Array[1, T] in general? Or have this be a Bits/Bit specific feature 2. Is there a way to avoid a circular import in this logic? The naive solution is to have Bit check if the driver is Bits[1], but this clearly requires a circular import. Perhaps we could use some sort of `T.convert_to(other_T)` API?
Codecov Report
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## master #1070 +/- ##
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+ Coverage 85.31% 85.33% +0.01%
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Files 144 144
Lines 15162 15178 +16
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+ Hits 12936 12952 +16
Misses 2226 2226
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I'm still not sure if we really want to support this pattern (our original ideas about type strictness). But if we do, I think we definitely should support all |
| @@ -113,11 +110,20 @@ def ite(self, t_branch, f_branch): | |||
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| @debug_wire | |||
| def wire(self, o, debug_info): | |||
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btw, why is this not in Digital? why do we need to override it in Bit?
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Right now this is just for Bit <-> Bits[1], if we wanted T <-> Array[1, T] then we would move it to Digital.
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Perhaps we can investigate other options with the designers to avoid the issue without making this fundamental change. |
rsetaluri
changed the title
3 participants
Two implementation issues:
a Bits/Bit specific feature
solution is to have Bit check if the driver is Bits[1], but this
clearly requires a circular import. Perhaps we could use some sort
of
T.convert_to(other_T)API?