Add missing $finish

pwmarcz · pwmarcz · commit 48f4b38f60a0 · 2018-11-25T12:57:03.000+01:00
diff --git a/verilog/adder_tb.v b/verilog/adder_tb.v
@@ -19,5 +19,6 @@ module Top;
       #5 x = 1; y = 0;
       #5 x = 0; y = 1;
       #5 x = 1; y = 1;
+      #5 $finish;
     end
 endmodule // Top
