[ExecuTorch][WebGPU] test: q4gsw shmem-GEMM prefill golden configs#20606
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/20606
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Pull Request resolved: #20606 **Add native fp64-golden configs that exercise the shared-memory tiled GEMM prefill route.** The existing `linear_q4gsw` prefill configs (`q_proj_4k`/`kv_proj_4k`, `K=2048`, `N<=2048`) all route to the register-tiled GEMM, so the new shmem GEMM route (`K >= 4096 || N >= 4096`) had no coverage. This adds three configs — kept in lockstep between `test_quantized_linear.py` `CONFIGS` and the C++ `kQ4gswConfigs` table — that exercise it (the op lands in the stacked diff below): - `gate_proj_pf` (`M128 K2048 N8192`) — shmem via large `N` (gate/up prefill). - `down_proj_pf` (`M128 K8192 N2048`) — shmem via large `K` (down prefill), looser big-K tol. - `shmem_edge` (`M130 K4096 N2056`) — partial 32-tile bounds (`M` and `N` not multiples of 32). Co-authored-with: Claude Code. ghstack-source-id: 398396337 @exported-using-ghexport Differential Revision: [D110095129](https://our.internmc.facebook.com/intern/diff/D110095129/)
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Stack from ghstack (oldest at bottom):
Add native fp64-golden configs that exercise the shared-memory tiled GEMM prefill route.
The existing
linear_q4gswprefill configs (q_proj_4k/kv_proj_4k,K=2048,N<=2048) all route to the register-tiled GEMM, so the new shmem GEMM route (K >= 4096 || N >= 4096) had no coverage. This adds three configs — kept in lockstep betweentest_quantized_linear.pyCONFIGSand the C++kQ4gswConfigstable — that exercise it (the op lands in the stacked diff below):gate_proj_pf(M128 K2048 N8192) — shmem via largeN(gate/up prefill).down_proj_pf(M128 K8192 N2048) — shmem via largeK(down prefill), looser big-K tol.shmem_edge(M130 K4096 N2056) — partial 32-tile bounds (MandNnot multiples of 32).Co-authored-with: Claude Code.
@exported-using-ghexport
Differential Revision: D110095129
Differential Revision: D110095129