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Fix: Update SPI PIO initialization to use 64-bit masks for RP2350B - #727
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peterharperuk
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Dec 17, 2025
lurch
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Jun 6, 2026
| gpio_set_outover(pin_sck, cpol ? GPIO_OVERRIDE_INVERT : GPIO_OVERRIDE_NORMAL); | ||
| // SPI is synchronous, so bypass input synchroniser to reduce input delay. | ||
| hw_set_bits(&pio->input_sync_bypass, 1u << pin_miso); | ||
| hw_set_bits(&pio->input_sync_bypass, (pin_miso >= 32) ? (1u << (pin_miso - 16)) : (1u << pin_miso)); |
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I'm not entirely sure that this is correct. You'll need to do the (pin_miso - 16) thing if the PIO has been remapped to the "upper pin range", which will indeed happen if (pin_miso >= 32); but there's a slight edge-case here where pin_miso might be less than 32, but one of the other pins (e.g. pin_sck) might be above 32? (which would also cause the PIO to use the "upper pin range")
So I think the correct fix here is actually:
hw_set_bits(&pio->input_sync_bypass, (1u << (pin_miso - pio_get_gpio_base(pio))));?
(but I've also suggested raspberrypi/pico-sdk#2986 to make this easier in future)
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Hi @lurch that seems to be correct rather than using magic number.
lurch
reviewed
Jun 6, 2026
| pio_gpio_init(pio, pin_sck + 1); | ||
| gpio_set_outover(pin_sck, cpol ? GPIO_OVERRIDE_INVERT : GPIO_OVERRIDE_NORMAL); | ||
| hw_set_bits(&pio->input_sync_bypass, 1u << pin_miso); | ||
| hw_set_bits(&pio->input_sync_bypass, (pin_miso >= 32) ? (1u << (pin_miso - 16)) : (1u << pin_miso)); |
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...and obviously the same applies here too 🙂
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This PR is a fix for Issue #725 to allow using the GPIOs>32 (typically for RP2350B variant). This pull request updates the SPI PIO initialisation functions to improve support for higher-numbered GPIO pins and 64-bit pin masks.
The main changes involve switching to 64-bit versions of pin mask functions and correcting the logic for bypassing input synchronisation on the MISO pin.