Skip to content
This repository has been archived by the owner on Aug 17, 2022. It is now read-only.

Add riscv-gvsoc.exp baseboard: target board for gvsoc simulator. #7

Open
wants to merge 1 commit into
base: riscv-dejagnu-1.6
Choose a base branch
from
Open
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions Makefile.am
Original file line number Diff line number Diff line change
Expand Up @@ -109,6 +109,7 @@ baseboard_DATA = \
baseboards/multi-sim.exp \
baseboards/powerpc-sim.exp \
baseboards/powerpcle-sim.exp \
baseboards/riscv-gvsoc.exp \
baseboards/riscv-sim.exp \
baseboards/riscv-sim-gdb.exp \
baseboards/riscv-sim-nano.exp \
Expand Down
28 changes: 28 additions & 0 deletions baseboards/riscv-gvsoc.exp
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
# Load the generic configuration for this board. This will define any
# routines needed to communicate with the board.
load_generic_config "sim"

set_board_info sim "gvsoc_sim"
set_board_info sim,options ""
set_board_info is_simulator 1

# No default multilib options are needed for this board.
process_multilib_options ""

set_board_info cflags ""

set_board_info ldflags "$::env(GVSOC_LD_FLAGS)"

# No linker script needed.
set_board_info ldscript ""

# No support for signals on this target.
set_board_info gdb,nosignals 1
set_board_info gcc,stack_size 32768

# L2 memory available without stack, heap and other segments (20kB)
set_board_info gcc,memory_size 435000


# Set timeout
set_board_info gcc,timeout 10