arc comments update

riscvarchive · Jun 6, 2022 · c5223d3 · c5223d3
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diff --git a/Zawrs.pdf b/Zawrs.pdf
diff --git a/header.adoc b/header.adoc
@@ -47,23 +47,23 @@ Assume everything can change. This draft specification will change before
 being accepted as standard, so implementations made to this draft 
 specification will likely not conform to the future standard.
 ====
-
 [preface]
-== Copyright and license information
+=== Copyright and license information
 This specification is licensed under the Creative Commons 
 Attribution 4.0 International License (CC-BY 4.0). The full 
 license text is available at
 https://creativecommons.org/licenses/by/4.0/.
 
 Copyright 2022 by RISC-V International.
 
+[preface]
 === Contributors
 
 This RISC-V specification has been contributed to directly or indirectly by:
 
 Aaron Durbin, Abel Bernabeu, Allen Baum, Christoph Müllner, David Weaver, Greg Favor, Josh Scheid, Ken Dockser, Paul Donahue, Phil McCoy, Philipp Tomsich, Tariq Kurd, Ved Shanbhogue
 
-=== Introduction
+== Introduction
 The Zawrs extension defines a pair of instructions to be used in polling loops 
 that allows a core to enter a low-power state and wait on a store to a memory 
 location. Waiting for a memory location to be updated is a common pattern in