Add qemu CI by KushalMeghani1644 · Pull Request #372 · rust-embedded/riscv

KushalMeghani1644 · 2025-11-14T11:39:09Z

This PR adds a Github Actions workflow to build and execute RISC-V examples on QEMU, enabling detection of runtime bugs that static compilation checks may miss.

This PR addresses issue #311

KushalMeghani1644 · 2025-11-14T12:18:59Z

ugh, I shall work on this more... thus I am making it a draft.

KushalMeghani1644 · 2025-11-14T13:43:48Z

Hola @romancardenas I tried to add QEMU CI here but things are getting way harder, I have done multiple fixes but I just want to make sure the fact that am I even going in the right direction? (sorry for the noise in this PR btw)

romancardenas · 2025-11-14T13:48:32Z

Adding QEMU to the CI is not that easy. You must create working examples that produce an output that you can then check with something like xtasks. Check how rtic does this.

You must find a set of "illustrative" targets (e.g., e310x for riscv32imc, something else for riscv64gc...) and run examples there.

Again, it is quite a complex task, and I suggest you to leave it until you get more expertise on these subjects.

KushalMeghani1644 · 2025-11-14T13:56:18Z

I see! Thanks for helping me out!! And I do agree/understand that setting up QEMU ci is very complex, but I feel it will be valuable challenge to give a shot. Even if it takes time, I think it would be fun learning experience! Appreciate your guidance!

romancardenas · 2025-11-14T14:20:17Z

Good luck with it! RTIC has a great CI that runs tests on Arm and RISC-V. You can learn a lot from their project. Also, you can check how the esp-rs folks do it.

KushalMeghani1644 · 2025-11-14T14:32:09Z

Thanks alot for your guidance! I appreciate it alot.

KushalMeghani1644 · 2025-11-15T07:14:33Z

HI @romancardenas I am sorry to ping you again & again... I tried a-lot to mirror the RTIC QEMU CI here and seeing the mixed results here... I need your help for further fixes and guidance for what I shall do next?

KushalMeghani1644 · 2025-11-15T08:04:51Z

well @romancardenas I did a re-check of the RTIC crate's QEMU CI... and seems like it was easily fixable... now I just need your guidance upon what shall I change/update or what's wrong and what not! Thanks for your review and sorry for the disturbances.

KushalMeghani1644 · 2025-11-28T09:55:15Z

@romancardenas sorry for the ping... but can you please help me figure out what to do here next... the QEMU CI passes... but I have a few doubts if the results are fine! Could you please review this once?

romancardenas · 2025-11-28T10:04:59Z

Hey @KushalMeghani1644

Sorry, but I currently have no time for advising and such activities. I can review contributions, but not helping people figure out how to add new functionalities. From what I can see, your QEMU tests are not useful, as the output is blank. You must set up a proper scenario with at least a working UART that allows us to print characters and check if the logic works.

Please, work out this locally, and once it works on your machine, push it here and check that it behaves exactly as it works on your machine.

KushalMeghani1644 · 2025-11-28T10:06:18Z

Alright! sorry to disturb you... I will work on this ASAP!

romancardenas · 2025-11-28T10:10:20Z

Forget about the UART!

Use riscv-semihosting instead. It should work out of the box en qemu if semihisting enabled

KushalMeghani1644 · 2025-11-28T10:51:05Z

OK, thanks for the suggestion @romancardenas ! I will use riscv-semihosting instead! and btw in my local test I was able to get this!

cargo run -p xtask -- qemu --target riscv32imac-unknown-none-elf --example hello
    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.03s
     Running `target/debug/xtask qemu --target riscv32imac-unknown-none-elf --example hello`
   Compiling riscv-rt v0.16.0 (/home/kushal/riscv/riscv-rt)
    Finished `release` profile [optimized] target(s) in 0.23s
HELLO_QEMU                                                                                                                      /2.5s
 cargo run -p xtask -- qemu --target riscv64gc-unknown-none-elf --example hello
    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.03s
     Running `target/debug/xtask qemu --target riscv64gc-unknown-none-elf --example hello`
   Compiling riscv-rt v0.16.0 (/home/kushal/riscv/riscv-rt)
    Finished `release` profile [optimized] target(s) in 0.24s
HELLO_QEMU

though this is indeed through UART... I will try and make it use riscv-semihosting!

romancardenas · 2025-11-28T10:59:54Z

Congrats! you are in the right track.

For this PR, two examples (one with UART, one with semihosting) could be enough. Using semihosting, you can make QEMU finish its execution so the CI can check the output with a baseline file to see if everything works as expected

Co-authored-by: Román Cárdenas Rodríguez <rcardenas.rod@gmail.com>

romancardenas · 2025-12-03T13:31:09Z

@@ -0,0 +1 @@
+Hello from semihosting!


Instead of having multiple identical files, I think it would be better to only have a ci/expected/<example.run> file.

You can implement a smarter xtask process that:

Checks if the ci/expected/<target>/<example>.run file exists. If so, use that file as golden file.

If file does not exist, use ci/expected/<example>.run

romancardenas · 2025-12-03T13:35:47Z

+        target:
+          - riscv32i-unknown-none-elf


Try something like this, I think it should work (not 100% sure about the correctness of the syntax):

Suggested change

target:

- riscv32i-unknown-none-elf

target-qemu:

- target: riscv32i-unknown-none-elf

qemu: riscv32

- target: ...

Then, in the examples, you can refer to the each element of the tuple as ${{ matrix.target-qemu.target }} and ${{ matrix.target-qemu.qemu }}

romancardenas · 2025-12-03T13:36:14Z

+        include:
+          - target: riscv32i-unknown-none-elf
+            qemu-system: riscv32
+          - target: riscv32im-unknown-none-elf
+            qemu-system: riscv32
+          - target: riscv32imc-unknown-none-elf
+            qemu-system: riscv32
+          - target: riscv32imac-unknown-none-elf
+            qemu-system: riscv32
+          - target: riscv32imafc-unknown-none-elf
+            qemu-system: riscv32
+          - target: riscv64imac-unknown-none-elf
+            qemu-system: riscv64
+          - target: riscv64gc-unknown-none-elf
+            qemu-system: riscv64


With the previous suggestion, this part is not required

Suggested change

include:

- target: riscv32i-unknown-none-elf

qemu-system: riscv32

- target: riscv32im-unknown-none-elf

qemu-system: riscv32

- target: riscv32imc-unknown-none-elf

qemu-system: riscv32

- target: riscv32imac-unknown-none-elf

qemu-system: riscv32

- target: riscv32imafc-unknown-none-elf

qemu-system: riscv32

- target: riscv64imac-unknown-none-elf

qemu-system: riscv64

- target: riscv64gc-unknown-none-elf

qemu-system: riscv64

romancardenas · 2025-12-03T13:41:16Z

+    if !expected_path.exists() {
+        fs::create_dir_all(expected_path.parent().unwrap())?;
+        fs::write(&expected_path, stdout.as_bytes())?;
+        bail!("expected output created; re-run CI");
+    }


Don't like the idea of automatically creating golden files. I think it should fail the test and inform the user that the reason of the fail is that a golden file does not exist.

Also, maybe here is where we can add the additional logic of: if golden file does not exist for this target, then check for the generic golden file

romancardenas · 2025-12-03T13:42:00Z

@@ -0,0 +1,11 @@
+MEMORY


Hey, this comment is not resolved! This file should be deleted. Only the device_virt.x file is required

romancardenas · 2025-12-03T13:43:09Z

+    fs,
+    path::PathBuf,
+    process::{Command, Stdio},
+    thread,


Please, make sure that the code does not have any warning in your PC. An unused reexport should trigger a warning

target-qemu matrix

KushalMeghani1644 · 2025-12-05T10:49:03Z

Hey @romancardenas I have fixed/updated the codes and the CI as instructed and have created the golden files as-well! hope the changes are fine!
Thanks for putting time to my PR

Sorry for the terrible commit history xD

romancardenas · 2025-12-05T11:10:30Z

The git history is all wrong. You are including changes from other PRs. Please, fix this and I will keep reviewing.

My suggestion is:

Start from a clean repo with the current master branch
Add only the changes related to QEMU CI
Open a new PR with clean changes so it makes my job easier.

KushalMeghani1644 · 2025-12-05T11:27:26Z

DONE! I have made the new PR @romancardenas with only 1 commit and the files that add the CI only, no spaghetti instead of commit history :)

KushalMeghani1644 requested a review from a team as a code owner November 14, 2025 11:39

KushalMeghani1644 marked this pull request as draft November 14, 2025 12:19

KushalMeghani1644 marked this pull request as ready for review November 15, 2025 08:54

KushalMeghani1644 added 11 commits November 26, 2025 16:24

Implement VSTOPI CSR for RISC-V

2f85419

Update CHANGELOG.md

770334a

Add qemu CI

f2149a3

Improve QEMU CI

105c9f4

Fix QEMU CI

ec4e7d4

Fix QEMU CI

b92ec05

Update QEMU CI

7d0d8df

Fix package issue

17d9bed

Add QEMU CI to add expected hello outputs

3637239

Fix qemu CI

8567f5f

Fix formatting

0078ff2

KushalMeghani1644 force-pushed the add-qemu-ci branch from d8062fb to 0078ff2 Compare November 26, 2025 11:19

Fix QEMU CI for a clean output ensuring the CI passes

1731bdf

KushalMeghani1644 and others added 14 commits December 3, 2025 18:14

Fix qemu CI

62bd0fb

Fix formatting

0792729

Fix QEMU CI for a clean output ensuring the CI passes

bb8684e

Updated tests to use riscv-semihosting instead of UART

eca57eb

Added one test using UART and one test with riscv-semihosting

6c48a60

Update CHANGELOG.md

66410a1

Update types.toml

fabc4cd

Update riscv-rt/examples/hello.rs

6bd28fc

Co-authored-by: Román Cárdenas Rodríguez <rcardenas.rod@gmail.com>

Update riscv-rt/examples/hello.rs

9288569

Co-authored-by: Román Cárdenas Rodríguez <rcardenas.rod@gmail.com>

Update riscv-rt/CHANGELOG.md

5a8fd70

Co-authored-by: Román Cárdenas Rodríguez <rcardenas.rod@gmail.com>

Update xtask/src/main.rs

1809192

Co-authored-by: Román Cárdenas Rodríguez <rcardenas.rod@gmail.com>

Address review comments

e516f04

fix formatting

e8e6847

Add expected QEMU CI files

1dab284

rust-embedded deleted a comment from Copilot AI Dec 3, 2025

romancardenas requested changes Dec 3, 2025

View reviewed changes

KushalMeghani1644 added 8 commits December 5, 2025 15:46

Simplify QEMU CI by consolidating golden files and using

4cbabfa

target-qemu matrix

Remove uneeded file

d56564b

resolve conflict

1e4763a

fix lints

7eed218

Remove conflicts

de5e0b9

Fix QEMU CI

7fbdf5a

Remove duplicates in code

5b4b717

Remove uneeded files

4bede74

KushalMeghani1644 requested a review from romancardenas December 5, 2025 10:49

romancardenas closed this Dec 5, 2025

KushalMeghani1644 mentioned this pull request Dec 5, 2025

Add QEMU CI support #378

Merged

-        target:
-          - riscv32i-unknown-none-elf
+        target-qemu:
+          - target: riscv32i-unknown-none-elf
+            qemu: riscv32
+          - target: ...

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