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riscv: asm: amend documents to mention Xuantie C907 core supported as…
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…sembly functions

Signed-off-by: Zhouqi Jiang <[email protected]>
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@luojia65
luojia65 committed Dec 15, 2024
1 parent fe7ec71 commit 5d0eeb4
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Showing 2 changed files with 34 additions and 22 deletions.
48 changes: 30 additions & 18 deletions xuantie-riscv/src/asm/xtheadcmo.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ use core::arch::asm;
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores.
/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores.
#[inline]
pub unsafe fn dcache_call() {
// th.dcache.call
Expand All @@ -37,7 +37,7 @@ pub unsafe fn dcache_call() {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores.
/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores.
#[inline]
pub unsafe fn dcache_iall() {
// th.dcache.iall
Expand All @@ -59,7 +59,7 @@ pub unsafe fn dcache_iall() {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores.
/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores.
#[inline]
pub unsafe fn dcache_ciall() {
// th.dcache.ciall
Expand All @@ -81,7 +81,7 @@ pub unsafe fn dcache_ciall() {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910, C906, E907, E906 and E902 cores.
/// This instruction is supported on Xuantie C910, C906, C907, E907, E906 and E902 cores.
#[inline]
pub unsafe fn icache_iall() {
// th.icache.iall
Expand All @@ -104,7 +104,7 @@ pub unsafe fn icache_iall() {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910 and C906 cores.
/// This instruction is supported on Xuantie C910, C906 and C907 cores.
#[inline]
pub unsafe fn icache_ialls() {
// th.icache.ialls
Expand Down Expand Up @@ -192,7 +192,7 @@ pub unsafe fn l2cache_ciall() {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores.
/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores.
///
/// The C910 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way,
/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13;
Expand All @@ -202,6 +202,10 @@ pub unsafe fn l2cache_ciall() {
/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13;
/// when configured 64 Kibibytes, `w` equals 14.
///
/// The C907 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way,
/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13;
/// when configured 64 Kibibytes, `w` equals 14.
///
/// The E907 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way,
/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13;
/// when configured 16 Kibibytes, `w` equals 12, and so on.
Expand Down Expand Up @@ -230,7 +234,7 @@ pub unsafe fn dcache_csw(way_and_set: usize) {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores.
/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores.
///
/// The C910 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way,
/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13;
Expand All @@ -240,6 +244,10 @@ pub unsafe fn dcache_csw(way_and_set: usize) {
/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13;
/// when configured 64 Kibibytes, `w` equals 14.
///
/// The C907 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way,
/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13;
/// when configured 64 Kibibytes, `w` equals 14.
///
/// The E907 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way,
/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13;
/// when configured 16 Kibibytes, `w` equals 12, and so on.
Expand Down Expand Up @@ -270,7 +278,7 @@ pub unsafe fn dcache_isw(way_and_set: usize) {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores.
/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores.
///
/// The C910 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way,
/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13;
Expand All @@ -280,6 +288,10 @@ pub unsafe fn dcache_isw(way_and_set: usize) {
/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13;
/// when configured 64 Kibibytes, `w` equals 14.
///
/// The C907 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way,
/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13;
/// when configured 64 Kibibytes, `w` equals 14.
///
/// The E907 core has a 2-way set-associative D-cache. Input variable `rs1[31]` represents number of way,
/// while `rs1[w:6]` represents number of set. When D-cache is configured 32 Kibibytes, `w` equals 13;
/// when configured 16 Kibibytes, `w` equals 12, and so on.
Expand Down Expand Up @@ -313,7 +325,7 @@ pub unsafe fn dcache_cisw(way_and_set: usize) {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910 and C906 cores.
/// This instruction is supported on Xuantie C910, C906 and C907 cores.
/// On Xuantie C906 User Manual, this instruction is named `DCACHE.CVA`.
#[inline]
pub unsafe fn dcache_cval1(va: usize) {
Expand Down Expand Up @@ -341,7 +353,7 @@ pub unsafe fn dcache_cval1(va: usize) {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910 core.
/// This instruction is supported on Xuantie C910 and C907 cores.
///
/// The Xuantie C906 User Manual names `DCACHE.CVAL1` as `DCACHE.CVA`; to clean dirty item on
/// C906 you may need to use function [`dcache_cval1`] on this library.
Expand Down Expand Up @@ -372,7 +384,7 @@ pub unsafe fn dcache_cva(va: usize) {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910 and C906 cores.
/// This instruction is supported on Xuantie C910, C906 and C907 cores.
#[inline]
pub unsafe fn dcache_iva(va: usize) {
// th.dcache.iva
Expand Down Expand Up @@ -403,7 +415,7 @@ pub unsafe fn dcache_iva(va: usize) {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910 and C906 cores.
/// This instruction is supported on Xuantie C910, C906 and C907 cores.
#[inline]
pub unsafe fn dcache_civa(va: usize) {
// th.dcache.civa
Expand All @@ -426,7 +438,7 @@ pub unsafe fn dcache_civa(va: usize) {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores.
/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores.
/// On Xuantie C906 User Manual, Xuantie E907 User Manual and Xuantie E906 User Manual,
/// this instruction is named `DCACHE.CPA`.
#[inline]
Expand All @@ -451,7 +463,7 @@ pub unsafe fn dcache_cpal1(pa: usize) {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910 core.
/// This instruction is supported on Xuantie C910 and C907 cores.
///
/// The Xuantie C906 User Manual, Xuantie E907 User Manual and Xuantie E906 User Manual
/// names `DCACHE.CPAL1` as `DCACHE.CPA`; to clean dirty item on
Expand All @@ -478,7 +490,7 @@ pub unsafe fn dcache_cpa(pa: usize) {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores.
/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores.
pub unsafe fn dcache_ipa(pa: usize) {
// th.dcache.ipa
asm!(".insn i 0x0B, 0, x0, {}, 0x02A", in(reg) pa)
Expand All @@ -501,7 +513,7 @@ pub unsafe fn dcache_ipa(pa: usize) {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores.
/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores.
#[inline]
pub unsafe fn dcache_cipa(pa: usize) {
// th.dcache.cipa
Expand Down Expand Up @@ -531,7 +543,7 @@ pub unsafe fn dcache_cipa(pa: usize) {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910 and C906 cores.
/// This instruction is supported on Xuantie C910, C906 and C907 cores.
#[inline]
pub unsafe fn icache_iva(va: usize) {
// th.icache.iva
Expand All @@ -554,7 +566,7 @@ pub unsafe fn icache_iva(va: usize) {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910, C906, E907, E906 and E902 cores.
/// This instruction is supported on Xuantie C910, C906, C907, E907, E906 and E902 cores.
#[inline]
pub unsafe fn icache_ipa(pa: usize) {
// th.icache.ipa
Expand Down
8 changes: 4 additions & 4 deletions xuantie-riscv/src/asm/xtheadsync.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ use core::arch::asm;
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores.
/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores.
#[inline]
pub unsafe fn sync() {
// th.sync
Expand All @@ -42,7 +42,7 @@ pub unsafe fn sync() {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910 core.
/// This instruction is supported on Xuantie C910 and C907 cores.
#[inline]
pub unsafe fn sync_s() {
// th.sync.s
Expand All @@ -66,7 +66,7 @@ pub unsafe fn sync_s() {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910, C906, E907 and E906 cores.
/// This instruction is supported on Xuantie C910, C906, C907, E907 and E906 cores.
#[inline]
pub unsafe fn sync_i() {
// th.sync.i
Expand All @@ -91,7 +91,7 @@ pub unsafe fn sync_i() {
///
/// # Platform support
///
/// This instruction is supported on Xuantie C910 core.
/// This instruction is supported on Xuantie C910 and C907 cores.
#[inline]
pub unsafe fn sync_is() {
// th.sync.is
Expand Down

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