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feat word hi-lo refactor #963

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feat word hi-lo refactor #963

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DreamWuGit
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@DreamWuGit DreamWuGit commented Sep 20, 2023

Description

upstream related PRs refer to https://hackmd.io/wLHeyWHjSAyVidSmkxsP9A?view

  • Evm circuit

    • update common gadgets(math gadgets, constrain builder, memory gadgets etc.)
    • update all opcodes
    • update all error cases
    • updates precompiles
    • update l1 fee gadgets etc. which not exists in upstream.
    • WIP testing & fix failures(default & scroll feature) , left mpt test failure
    • fixing precompiles.
    • adjust MAX_STEP_HEIGHT +1 to make end_block still occupy height 1 day
    • rebase & resolve conflict with latest develop branch(precompiles, begin_tx etc.)
  • state circuit

    • update constrain builders, multi precise integer , lexicographic ordering modules
    • remove rlc module and update randomness with word directly
    • update dev & test modules
    • MPT updates proof related
    • fix degree increase
  • copy circuit

    • update src_id, dst_id lookup with word type
    • update word_rlc, word_prev_rlc
  • mpt circuit

    • update mpt related key value to word type
    • testing & fix issue
  • bytecode circuit

    • update bytecode table codehash -> word
    • update bytecode circuit / bytecode row
    • update to_poseidon_hash circuit, add new column and constrain lo hi
  • keccak circuit

    • update keccak table output_rlc --> word
  • pi circuit

    • update state root
  • sig circuit

    • update per keccak table change

Issue Link

[link issue here]

Type of change

  • Bug fix (non-breaking change which fixes an issue)
  • New feature (non-breaking change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to not work as expected)
  • This change requires a documentation update

@darth-cy darth-cy mentioned this pull request Oct 2, 2023
4 tasks
@darth-cy darth-cy mentioned this pull request Oct 8, 2023
4 tasks
darth-cy and others added 18 commits October 9, 2023 13:27
* temporarily comment out rlc

* correct modulo
and ec mul

* correct import

* rlc from word limbs:

* fix ec mul

* ec mul adapt rlc pattern

* change ecrecover structs

* correct parts of ecrecover gadget

* fix modulo conflict

* fix precompile failed error state

* remove import

* fix precompile gadget

* fit lt_word

* remove import

* remove import

* remove import

* fix callop

* remove import

* fix modulo

* restore rlc

* minor math fix

* fix lt generic

* remove lt word cell type

* fix lt word gadget related code

* fix modulo

* fix ecrecover constants

* remove import

---------

Co-authored-by: DreamWuGit <[email protected]>
@lispc
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lispc commented Jan 28, 2024

mask.require_equal_unaligned_word(value: RlcCell, left: Word, right: Word) should also be changed to mask.require_equal_unaligned_word(value: Word, left: Word, right: Word).

@DreamWuGit
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mask.require_equal_unaligned_word(value: RlcCell, left: Word, right: Word) should also be changed to mask.require_equal_unaligned_word(value: Word, left: Word, right: Word).

will have a look.

@DreamWuGit
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DreamWuGit commented Jan 30, 2024

mask.require_equal_unaligned_word(value: RlcCell, left: Word, right: Word) should also be changed to mask.require_equal_unaligned_word(value: Word, left: Word, right: Word).

will have a look.

updated to new helper signature require_equal_unaligned_word(value: &Word, left: &Word, right: &Word) in 8084fc0 although rlc was used internally in this method. it is not easy to remove rlc now at small code changes.

@lispc
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lispc commented Jan 30, 2024

mask.require_equal_unaligned_word(value: RlcCell, left: Word, right: Word) should also be changed to mask.require_equal_unaligned_word(value: Word, left: Word, right: Word).

will have a look.

updated to new helper signature require_equal_unaligned_word(value: &Word, left: &Word, right: &Word) in 8084fc0 although rlc was used internally in this method. it is not easy to remove rlc now at small code changes.

ok let it be stage3

@DreamWuGit
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\b run testool 1

@DreamWuGit
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\b run testool

@lispc
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lispc commented Jan 30, 2024

i am running testool (default mode, nightly suite, evm + state + copy circuits)

@DreamWuGit
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see conflicts again, need to sync & merge..

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6 participants