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  1. FIR-filter-for-FPGA-Zybo FIR-filter-for-FPGA-Zybo Public

    As part of the laboratory exercise of Dig. VSLI in ECE NTUA, me and Ioannis Danias, we designed in VHDL, a FIR filter for the Zybo board which communicates with it via AXI LITE.

    VHDL 2

  2. TollAnalysisWebApp TollAnalysisWebApp Public

    TollAnalysisWebApp with NODEjs, REACTjs, MYSQL, SCIKIT-LEARN

    JavaScript