Add support for flash.rs on bigger chips #168
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maximeborges
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See #167 (comment). |
hannobraun
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Feb 8, 2022
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Thanks again, @maximeborges!
How confident are you in this change? I don't have a test setup ready, don't really understand what this does, and don't have the time to study up in the reference manual.
If you're happy with your testing and your understanding this change, that's good enough for me. If this requires more testing, I can add a help wanted label.
Also, CI is failing, due to formatting. Running cargo fmt should fix that.
Once CI is green and you give me the go-ahead regarding my questions above, I'm happy to merge.
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I confirm that this example works on my Nucleo-F767ZI |
hannobraun
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Feb 8, 2022
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The current code to erase flash is only using the
merfield.On bigger chips, there is two memory banks, so the
merfield is split in two for the two memory banks,mer1andmer2.This PR add checks to configure either
merormer[12]for erase functions.