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Merge pull request #305 from tactcomplabs/Zmmul
Zmmul extension
2 parents 1484539 + 8f56671 commit 9af3bd4

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5 files changed

+41
-25
lines changed

5 files changed

+41
-25
lines changed

‎include/RevFeature.h

+5-4
Original file line numberDiff line numberDiff line change
@@ -38,10 +38,11 @@ enum RevFeatureType : uint32_t {
3838
RV_ZICBOM = 1 << 12, ///< RevFeatureType: Zicbom-extension
3939
RV_ZICSR = 1 << 13, ///< RevFEatureType: Zicsr-extension
4040
RV_ZIFENCEI = 1 << 14, ///< RevFeatureType: Zifencei-extension
41-
RV_ZFA = 1 << 15, ///< RevFeatureType: Zfa-extension
42-
RV_ZFH = 1 << 16, ///< RevFeatureType: H-extension
43-
RV_ZFHMIN = 1 << 17, ///< RevFeatureRtpe: Zfhmin extension
44-
RV_ZTSO = 1 << 18, ///< RevFeatureType: Ztso-extension
41+
RV_ZMMUL = 1 << 15, ///< RevFeatureType: Zmmul-extension
42+
RV_ZFA = 1 << 16, ///< RevFeatureType: Zfa-extension
43+
RV_ZFH = 1 << 17, ///< RevFeatureType: H-extension
44+
RV_ZFHMIN = 1 << 18, ///< RevFeatureRtpe: Zfhmin extension
45+
RV_ZTSO = 1 << 19, ///< RevFeatureType: Ztso-extension
4546
};
4647

4748
class RevFeature {

‎include/insns/RV32M.h

+7
Original file line numberDiff line numberDiff line change
@@ -56,16 +56,23 @@ class RV32M : public RevExt {
5656
RevMInstDefaults().SetMnemonic("mulh %rd, %rs1, %rs2" ).SetFunct3(0b001).SetImplFunc(mulh ),
5757
RevMInstDefaults().SetMnemonic("mulhsu %rd, %rs1, %rs2").SetFunct3(0b010).SetImplFunc(mulhsu),
5858
RevMInstDefaults().SetMnemonic("mulhu %rd, %rs1, %rs2" ).SetFunct3(0b011).SetImplFunc(mulhu ),
59+
};
60+
61+
std::vector<RevInstEntry> RV32DivTable = {
5962
RevMInstDefaults().SetMnemonic("div %rd, %rs1, %rs2" ).SetFunct3(0b100).SetImplFunc(div ),
6063
RevMInstDefaults().SetMnemonic("divu %rd, %rs1, %rs2" ).SetFunct3(0b101).SetImplFunc(divu ),
6164
RevMInstDefaults().SetMnemonic("rem %rd, %rs1, %rs2" ).SetFunct3(0b110).SetImplFunc(rem ),
6265
RevMInstDefaults().SetMnemonic("remu %rd, %rs1, %rs20" ).SetFunct3(0b111).SetImplFunc(remu ),
6366
};
67+
6468
// clang-format on
6569

6670
public:
6771
/// RV32M: standard constructor
6872
RV32M( RevFeature* Feature, RevMem* RevMem, SST::Output* Output ) : RevExt( "RV32M", Feature, RevMem, Output ) {
73+
if( Feature->IsModeEnabled( RV_M ) ) {
74+
RV32MTable.insert( RV32MTable.end(), RV32DivTable.begin(), RV32DivTable.end() );
75+
}
6976
SetTable( std::move( RV32MTable ) );
7077
}
7178
}; // end class RV32I

‎include/insns/RV64M.h

+6
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,9 @@ class RV64M : public RevExt {
4646
// clang-format off
4747
std::vector<RevInstEntry> RV64MTable = {
4848
Rev64MInstDefaults().SetMnemonic("mulw %rd, %rs1, %rs2" ).SetFunct3(0b000).SetImplFunc(mulw) ,
49+
};
50+
51+
std::vector<RevInstEntry> RV64DivTable = {
4952
Rev64MInstDefaults().SetMnemonic("divw %rd, %rs1, %rs2" ).SetFunct3(0b100).SetImplFunc(divw) ,
5053
Rev64MInstDefaults().SetMnemonic("divuw %rd, %rs1, %rs2").SetFunct3(0b101).SetImplFunc(divuw),
5154
Rev64MInstDefaults().SetMnemonic("remw %rd, %rs1, %rs2" ).SetFunct3(0b110).SetImplFunc(remw) ,
@@ -56,6 +59,9 @@ class RV64M : public RevExt {
5659
public:
5760
/// RV64M: standard constructor
5861
RV64M( RevFeature* Feature, RevMem* RevMem, SST::Output* Output ) : RevExt( "RV64M", Feature, RevMem, Output ) {
62+
if( Feature->IsModeEnabled( RV_M ) ) {
63+
RV64MTable.insert( RV64MTable.end(), RV64DivTable.begin(), RV64DivTable.end() );
64+
}
5965
SetTable( std::move( RV64MTable ) );
6066
}
6167
}; // end class RV32I

‎src/RevCore.cc

+1-1
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,7 @@ bool RevCore::SeedInstTable() {
161161
}
162162

163163
// M Extension
164-
if( feature->IsModeEnabled( RV_M ) ) {
164+
if( feature->IsModeEnabled( RV_ZMMUL ) ) {
165165
EnableExt( new RV32M( feature, mem, output ) );
166166
if( feature->IsRV64() ) {
167167
EnableExt( new RV64M( feature, mem, output ) );

‎src/RevFeature.cc

+22-20
Original file line numberDiff line numberDiff line change
@@ -55,26 +55,28 @@ bool RevFeature::ParseMachineModel() {
5555
///<
5656
///< ExtensionName DefaultMajor DefaultMinor MinSupportedVersion MaxSupportedVersion Flags
5757
static constexpr std::tuple<std::string_view, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t> table[] = {
58-
{ "I", 2, 1, 2, 2, RV_I },
59-
{ "E", 2, 0, -1, 0, RV_E }, // Unsupported
60-
{ "M", 2, 0, 2, 2, RV_M },
61-
{ "A", 2, 1, 2, 2, RV_A },
62-
{ "F", 2, 2, 2, 2, RV_F | RV_ZICSR },
63-
{ "D", 2, 2, 2, 2, RV_D | RV_F | RV_ZICSR },
64-
{ "G", 2, 0, 2, 2, RV_I | RV_M | RV_A | RV_F | RV_D | RV_ZICSR | RV_ZIFENCEI },
65-
{ "Q", 2, 2, -1, 0, RV_Q | RV_D | RV_F | RV_ZICSR }, // Unsupported
66-
{ "C", 2, 0, 2, 2, RV_C },
67-
{ "B", 1, 0, -1, 0, RV_B }, // Unsupported
68-
{ "P", 0, 2, -1, 0, RV_P }, // Unsupported
69-
{ "V", 1, 0, -1, 0, RV_V | RV_D | RV_F | RV_ZICSR },
70-
{ "H", 1, 0, -1, 0, RV_H }, // Unsupported
71-
{ "Zicbom", 1, 0, 1, 1, RV_ZICBOM },
72-
{ "Zicsr", 2, 0, 2, 2, RV_ZICSR },
73-
{ "Zifencei", 2, 0, 2, 2, RV_ZIFENCEI },
74-
{ "Zfa", 1, 0, 1, 1, RV_ZFA | RV_F | RV_ZICSR }, // Unsupported
75-
{ "Zfh", 1, 0, -1, 0, RV_ZFH | RV_ZFHMIN | RV_F | RV_ZICSR }, // Unsupported
76-
{ "Zfhmin", 1, 0, -1, 0, RV_ZFHMIN | RV_F | RV_ZICSR }, // Unsupported
77-
{ "Ztso", 1, 0, -1, 0, RV_ZTSO }, // Unsupported
58+
{ "I", 2, 1, 2, 2, RV_I },
59+
{ "E", 2, 0, -1, 0, RV_E }, // Unsupported
60+
{ "M", 2, 0, 2, 2, RV_M | RV_ZMMUL },
61+
{ "A", 2, 1, 2, 2, RV_A },
62+
{ "F", 2, 2, 2, 2, RV_F | RV_ZICSR },
63+
{ "D", 2, 2, 2, 2, RV_D | RV_F | RV_ZICSR },
64+
{ "G", 2, 0, 2, 2, RV_I | RV_M | RV_ZMMUL | RV_A |
65+
RV_F | RV_D | RV_ZICSR | RV_ZIFENCEI },
66+
{ "Q", 2, 2, -1, 0, RV_Q | RV_D | RV_F | RV_ZICSR }, // Unsupported
67+
{ "C", 2, 0, 2, 2, RV_C },
68+
{ "B", 1, 0, -1, 0, RV_B }, // Unsupported
69+
{ "P", 0, 2, -1, 0, RV_P }, // Unsupported
70+
{ "V", 1, 0, -1, 0, RV_V | RV_D | RV_F | RV_ZICSR },
71+
{ "H", 1, 0, -1, 0, RV_H }, // Unsupported
72+
{ "Zicbom", 1, 0, 1, 1, RV_ZICBOM },
73+
{ "Zicsr", 2, 0, 2, 2, RV_ZICSR },
74+
{ "Zifencei", 2, 0, 2, 2, RV_ZIFENCEI },
75+
{ "Zmmul", 1, 0, 1, 1, RV_ZMMUL },
76+
{ "Zfa", 1, 0, 1, 1, RV_ZFA | RV_F | RV_ZICSR }, // Unsupported
77+
{ "Zfh", 1, 0, -1, 0, RV_ZFH | RV_ZFHMIN | RV_F | RV_ZICSR }, // Unsupported
78+
{ "Zfhmin", 1, 0, -1, 0, RV_ZFHMIN | RV_F | RV_ZICSR }, // Unsupported
79+
{ "Ztso", 1, 0, -1, 0, RV_ZTSO }, // Unsupported
7880
};
7981
// clang-format on
8082

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