Audio: ARIA: Add HiFi5 implementation

[andrula-song]

Add HiFi5 implementation of aria algorithm functions, compared with HiFi3 version, can reduce about 10% cycles.

[andrula-song]

here is the xtensa simulator result:

compared with hifi3 version, the HiFi5 version can save:
about 5% for aria_algo_get_data_odd_channel;
about 10% for aria_algo_get_data_even_channel;
about 15% for aria_algo_calc_gain.

[lgirdwood]

this is being cast to a uint32_t in the code and should simplify the L32 loads

[andrula-song]

from the xtensa simulator I didn't see any improvement, the purpose I use the uint8_t is to save memory. But it is okay to change it to a uint32_t table if we don't mind the memory usage.

[lgirdwood]

interesting, the L32 of a uint32_t is 1 op, but to load a byte is a L32 and a shift/mask.

[btian1]

@lgirdwood @andrula-song , there is load byte instruction, so no need use load32 for this table, save memory is always good:

Load 8-bit Unsigned L8UI
Xtensa Instruction Set Architecture (ISA) Reference Manual 449
Instruction Word (RRI8)
Required Configuration Option
Core Architecture (See Section 4.2 on page 51)
Assembler Syntax
L8UI at, as, 0..255
Description
L8UI is an 8-bit unsigned load from memory. It forms a virtual address by adding the
contents of address register as and an 8-bit zero-extended constant value encoded in
the instruction word. Therefore, the offset ranges from 0 to 255. Eight bits (one byte) are
read from the physical address. This data is then zero-extended and written to address
register at.
If the Region Translation Option (page 185) or the MMU Option (page 199)is enabled,
the virtual address is translated to the physical address. If not, the physical address is
identical to the virtual address. If the translation or memory reference encounters an
error (for example, protection violation or non-existent memory), the processor raises
one of several exceptions (see Section 4.4.2.5 on page 105)

[lgirdwood]

@singalsu needs your review.

[singalsu]

This looks like modulo 10 for 0 to 23 index. Likely not possible but if gains gains table size ARIA_MAX_GAIN_STATES could be 16 or other 2^N value this could be bit-and instead of modulo. But it's out-of-scope of this PR to change functionality.

[singalsu]

This looks like modulo 10 for 0 to 23 index. Likely not possible while keeping the algorithm the same but if gains gains table size ARIA_MAX_GAIN_STATES could be 16 or other 2^N value this could be bit-and instead of modulo. But it's out-of-scope of this PR to change functionality.

[singalsu]

Looks good to me, I got the patch and compared to aria_hifi3.c.

[singalsu]

This looks like modulo 10 for 0 to 23 index. Likely not possible while keeping the algorithm the same but if gains gains table size ARIA_MAX_GAIN_STATES could be 16 or other 2^N value this could be bit-and instead of modulo. But it's out-of-scope of this PR to change functionality.

[marc-hb]

Please switch to the new, de-duplicated approach from #8787