WIP: ULX3S support

.gitignore

@@ -8,3 +8,9 @@ synlog.tcl
 gerbers/
 build/
 *.pyc
+*.bit
+*.json
+.*.d
+.*.sw*
+gmon.out
+*.bin

boards/TinyFPGA_BX/Makefile

@@ -22,12 +22,22 @@ PKG = cm81
 
 all: $(PROJ).rpt fw.bin
 
+%.json: %.v ../../common/*.v 
+	yosys -q -p 'synth_ice40 -top $(PROJ) -json $@' $^
 %.blif: %.v ../../common/*.v 
-	yosys -p 'synth_ice40 -top $(PROJ) -blif $@' $^
+	yosys -q -p 'synth_ice40 -top $(PROJ) -blif $@' $^
 
-%.asc: $(PIN_DEF) %.blif
+NO-%.asc: $(PIN_DEF) %.blif
 	arachne-pnr -d 8k -P $(PKG) -o $@ -p $^
 
+%.asc: $(PIN_DEF) %.json
+	nextpnr-ice40 \
+		--$(DEVICE) \
+		--package $(PKG) \
+		--asc $@ \
+		--pcf $(PIN_DEF) \
+		--json $(basename $@).json \
+
 %.bin: %.asc
 	icepack $< $@
 

boards/TinyFPGA_BX/bootloader.v

@@ -20,6 +20,8 @@ module bootloader (
   ////////////////////////////////////////////////////////////////////////////////
   ////////////////////////////////////////////////////////////////////////////////
   wire clk_48mhz;
+  wire lock;
+  wire reset = !lock;
 
   SB_PLL40_CORE #(
     .DIVR(4'b0000),
@@ -43,13 +45,18 @@ module bootloader (
     .RESETB(1'b1),
     .BYPASS(1'b0),
     .LATCHINPUTVALUE(),
-    .LOCK(),
+    .LOCK(lock),
     .SDI(),
     .SDO(),
     .SCLK()
   );
 
+	reg clk_24mhz;
+	reg clk_12mhz;
+	always @(posedge clk_48mhz) clk_24mhz = !clk_24mhz;
+	always @(posedge clk_24mhz) clk_12mhz = !clk_12mhz;
 
+	wire clk = clk_12mhz; // quarter speed clock
 
   ////////////////////////////////////////////////////////////////////////////////
   ////////////////////////////////////////////////////////////////////////////////
@@ -74,7 +81,6 @@ module bootloader (
   ////////
   ////////////////////////////////////////////////////////////////////////////////
   ////////////////////////////////////////////////////////////////////////////////
-  wire reset;
   wire usb_p_tx;
   wire usb_n_tx;
   wire usb_p_rx;
@@ -85,6 +91,7 @@ module bootloader (
 
   tinyfpga_bootloader tinyfpga_bootloader_inst (
     .clk_48mhz(clk_48mhz),
+    .clk(clk),
     .reset(reset),
     .usb_p_tx(usb_p_tx),
     .usb_n_tx(usb_n_tx),
@@ -100,44 +107,38 @@ module bootloader (
   );
 
   assign pin_pu = 1'b1;
+  wire usb_p_rx_io;
+  wire usb_n_rx_io;
   assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_rx_io;
   assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_rx_io;
 
-  SB_IO #(
-     .PIN_TYPE(6'b101001),
-     .PULLUP(1'b0),
-     .NEG_TRIGGER(1'b0),
-     .IO_STANDARD("SB_LVCMOS")
-   ) io_dp_I (
-     .PACKAGE_PIN(pin_usbp),
-     .LATCH_INPUT_VALUE(1'b0),
-     .CLOCK_ENABLE(1'b1),
-     .INPUT_CLK(1'b0),
-     .OUTPUT_CLK(1'b0),
-     .OUTPUT_ENABLE(usb_tx_en),
-     .D_OUT_0(usb_p_tx),
-     .D_OUT_1(1'b0),
-     .D_IN_0(usb_p_rx_io),
-     .D_IN_1()
+  tristate usbn_buffer(
+	.pin(pin_usbn),
+	.enable(usb_tx_en),
+	.data_in(usb_n_rx_io),
+	.data_out(usb_n_tx)
   );
 
-  SB_IO #(
-     .PIN_TYPE(6'b101001),
-     .PULLUP(1'b0),
-     .NEG_TRIGGER(1'b0),
-     .IO_STANDARD("SB_LVCMOS")
-   ) io_dn_I (
-     .PACKAGE_PIN(pin_usbn),
-     .LATCH_INPUT_VALUE(1'b0),
-     .CLOCK_ENABLE(1'b1),
-     .INPUT_CLK(1'b0),
-     .OUTPUT_CLK(1'b0),
-     .OUTPUT_ENABLE(usb_tx_en),
-     .D_OUT_0(usb_n_tx),
-     .D_OUT_1(1'b0),
-     .D_IN_0(usb_n_rx_io),
-     .D_IN_1()
+  tristate usbp_buffer(
+	.pin(pin_usbp),
+	.enable(usb_tx_en),
+	.data_in(usb_p_rx_io),
+	.data_out(usb_p_tx)
   );
+endmodule
 
-  assign reset = 1'b0; 
+module tristate(
+  inout pin,
+  input enable,
+  input data_out,
+  output data_in
+);
+  SB_IO #(
+    .PIN_TYPE(6'b1010_01) // tristatable output
+  ) buffer(
+    .PACKAGE_PIN(pin),
+    .OUTPUT_ENABLE(enable),
+    .D_IN_0(data_in),
+    .D_OUT_0(data_out)
+  );
 endmodule

boards/TinyFPGA_BX/pins.pcf

@@ -3,46 +3,46 @@
 # Package:            CM81
 ###############################################################################
 
-#set_io pin_1 A2
-#set_io pin_2 A1
-#set_io pin_3 B1
-#set_io pin_4 C2
-#set_io pin_5 C1
-#set_io pin_6 D2
-#set_io pin_7 D1
-#set_io pin_8 E2
-#set_io pin_9 E1
-#set_io pin_10 G2
-#set_io pin_11 H1
-#set_io pin_12 J1
-#set_io pin_13 H2
-#set_io pin_14 H9
-#set_io pin_15 D9
-#set_io pin_16 D8
-#set_io pin_17 C9
-#set_io pin_18 A9
-#set_io pin_19 B8
-#set_io pin_20 A8
-#set_io pin_21 B7
-#set_io pin_22 A7
-#set_io pin_23 B6
-#set_io pin_24 A6
-#set_io pin_25 G1
-#set_io pin_26 J3
-#set_io pin_27 J4
-#set_io pin_28 H4
-set_io pin_29_miso H7
-set_io pin_30_cs F7
-set_io pin_31_mosi G6
-set_io pin_32_sck G7
-#set_io pin_33 J8
-#set_io pin_34 G9
-#set_io pin_35 J9
-#set_io pin_36 E8
-#set_io pin_37 J2
-set_io pin_led B3
-set_io pin_usbp B4
-set_io pin_usbn A4
-set_io pin_pu A3
-set_io pin_clk B2
+set_io -nowarn pin_1 A2
+set_io -nowarn pin_2 A1
+set_io -nowarn pin_3 B1
+set_io -nowarn pin_4 C2
+set_io -nowarn pin_5 C1
+set_io -nowarn pin_6 D2
+set_io -nowarn pin_7 D1
+set_io -nowarn pin_8 E2
+set_io -nowarn pin_9 E1
+set_io -nowarn pin_10 G2
+set_io -nowarn pin_11 H1
+set_io -nowarn pin_12 J1
+set_io -nowarn pin_13 H2
+set_io -nowarn pin_14 H9
+set_io -nowarn pin_15 D9
+set_io -nowarn pin_16 D8
+set_io -nowarn pin_17 C9
+set_io -nowarn pin_18 A9
+set_io -nowarn pin_19 B8
+set_io -nowarn pin_20 A8
+set_io -nowarn pin_21 B7
+set_io -nowarn pin_22 A7
+set_io -nowarn pin_23 B6
+set_io -nowarn pin_24 A6
+set_io -nowarn pin_25 G1
+set_io -nowarn pin_26 J3
+set_io -nowarn pin_27 J4
+set_io -nowarn pin_28 H4
+set_io -nowarn pin_29_miso H7
+set_io -nowarn pin_30_cs F7
+set_io -nowarn pin_31_mosi G6
+set_io -nowarn pin_32_sck G7
+set_io -nowarn pin_33 J8
+set_io -nowarn pin_34 G9
+set_io -nowarn pin_35 J9
+set_io -nowarn pin_36 E8
+set_io -nowarn pin_37 J2
+set_io -nowarn pin_led B3
+set_io -nowarn pin_usbp B4
+set_io -nowarn pin_usbn A4
+set_io -nowarn pin_pu A3
+set_io -nowarn pin_clk B2
 

boards/ULX3S/Makefile

@@ -0,0 +1,59 @@
+#
+# Bootloader for the ulx3s ECP5 board
+# Builds with nextpnr-ecp5 and prjtrellis from git as of 2019-07-05
+#
+IDCODE ?= 0x21111043 # 12f
+
+all: fw.bin
+
+flash: fw.bin bootloader.bit
+	@echo "-- Plug in both USB ports on the ecp5 --"
+	ujprog bootloader.bit
+	sleep 2
+	tinyprog -a 1 --security boardmeta.json
+	tinyprog -a 2 --security bootmeta.json
+	tinyprog -a 0 --program-image fw.bin
+	sleep 5
+	tinyprog -m
+
+fw.bin: bootloader.bit
+	ecpmulti \
+		--input-idcode 0x41111043 \
+		--output-idcode $(IDCODE) \
+		-v \
+		--output $@ \
+		--flashsize 128 \
+		--input $< \
+		--address 0x100000 \
+		--input $<
+
+
+%.json: %.v
+	yosys \
+		-p "read_verilog -I../../common $<" \
+		-p "synth_ecp5 -json $@" \
+		-E .$(basename $@).d \
+		-q \
+
+%.config: %.json
+	nextpnr-ecp5 \
+		--json $< \
+		--textcfg $@ \
+		--lpf ulx3s_v20.lpf \
+		--timing-allow-fail \
+		--25k
+
+%.bit: %.config
+	ecppack --idcode $(IDCODE) $< $@
+
+%.svf: %.config
+	ecppack --idcode $(IDCODE) --input $< --svf $@
+
+%.flash: %.bit
+	ujprog $<
+%.terminal: %.bit
+	ujprog -t -b 3000000 $<
+
+clean:
+	$(RM) *.config *.bit .*.d *.svf
+-include .*.d

boards/ULX3S/README.md

@@ -0,0 +1,23 @@
+ULX3S ECP5 FPGA
+---
+
+To bootstrap the bootloader:
+
+* `make` should build `bootloader.bit`
+* Connect both USB ports `US1` and `US2` to the computer
+* `sudo ujprog bootloader.bit` will load it into the FPGA SRAM via US1
+* The TinyFPGA bootloader should enumerate as `/dev/ttyACM0` via US2
+* Load the security pages into the SPI flash SFDP pages:
+```
+sudo tinyprog -a 1 --security boardmeta.json
+sudo tinyprog -a 2 --security bootmeta.json
+```
+* `tinyprog -m` should now show the meta data
+* `tinyprog -a 0 --program-image fw.bin` should write the multiboot image into the flash
+* Disconnect both the USB ports and reconnect just US2.
+* The bootloader should be running and flashing LED0, and show up again as `/dev/ttyACM0`
+* Load your own user image with `tinyprog -p userimage.bit`
+
+----
+
+Maybe that no longer works?  Had to write the 

boards/ULX3S/boardmeta.json

@@ -0,0 +1,6 @@
+{"boardmeta":{
+  "name": "ULX3S",
+  "fpga": "ecp5-12f",
+  "hver": "1.0.0",
+  "serial": 31415
+}}