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Code for ee290 lab3
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‎software/gemmini-tests-ee290.json

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{
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"name" : "gemmini-tests-ee290",
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"workdir" : ".",
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"base" : "br-base.json",
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"overlay" : "overlay",
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"host-init" : "host-init.sh",
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"command": "/root/run-tests-ee290.sh"
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}

‎software/overlay/root/run-tests-ee290.sh

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#!/usr/bin/env bash
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echo "*****************TEST RESULTS*************" > test_output.txt
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echo "=========very_large_matmul========="
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echo "=========very_large_matmul=========" >> test_output.txt
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/root/ee290/very_large_matmul-linux >> test_output.txt
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echo "=========CIFAR DNN========="
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echo "=========CIFAR DNN=========" >> test_output.txt
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/root/ee290/cifar_quant-linux >> test_output.txt
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echo "========Multi-Level Perceptron 1========="
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echo "========Multi-Level Perceptron 1=========" >> test_output.txt
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/root/mlps/mlp1-linux >> test_output.txt
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echo "========Multi-Level Perceptron 2========="
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echo "========Multi-Level Perceptron 2=========" >> test_output.txt
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/root/mlps/mlp2-linux >> test_output.txt
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echo "========MobileNet========="
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echo "========MobileNet=========" >> test_output.txt
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/root/imagenet/mobilenet-linux >> test_output.txt
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echo "========ResNet50========="
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echo "========ResNet50=========" >> test_output.txt
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/root/imagenet/resnet50-linux >> test_output.txt
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cat test_output.txt
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poweroff -f

‎src/main/resources/vsrc/MeshBlackBox.v

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// This is the blackbox we are asking you to implement
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// Assume TILEROWS=1, and TILECOLUMNS=1
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module MeshBlackBox
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#(parameter MESHROWS, MESHCOLUMNS, INPUT_BITWIDTH, OUTPUT_BITWIDTH, MAX_SIM_MM_LOG, ACC_BITWIDTH_LOG, TILEROWS=1, TILECOLUMNS=1)
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(
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input clock,
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input reset,
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input signed [INPUT_BITWIDTH-1:0] in_a[MESHROWS-1:0][TILEROWS-1:0],
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input signed [INPUT_BITWIDTH-1:0] in_d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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input signed [INPUT_BITWIDTH-1:0] in_b[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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input in_control_dataflow[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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input in_control_propagate[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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input [ACC_BITWIDTH_LOG-1:0] in_control_shift[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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input in_valid[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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input [MAX_SIM_MM_LOG-1:0] in_id[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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input in_last[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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output signed [OUTPUT_BITWIDTH-1:0] out_c[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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output signed [OUTPUT_BITWIDTH-1:0] out_b[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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output out_valid[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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output out_control_dataflow[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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output out_control_propagate[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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output [ACC_BITWIDTH_LOG-1:0] out_control_shift[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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output [MAX_SIM_MM_LOG-1:0] out_id[MESHCOLUMNS-1:0][TILECOLUMNS-1:0],
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output out_last[MESHCOLUMNS-1:0][TILECOLUMNS-1:0]
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);
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// ---------------------------------------------------------
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// ---------------------------------------------------------
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// DO NOT MODIFY ANYTHING ABOVE THIS
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// ---------------------------------------------------------
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// ---------------------------------------------------------
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//**********************************************************
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//**********************************************************
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//**********************************************************
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//******************** FILL THIS ***************************
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//**********************************************************
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//**********************************************************
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//**********************************************************
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endmodule // MeshBlackBox
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//**********************************************************
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//**********************************************************
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//**********************************************************
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//********** FEEL FREE TO ADD MODULES HERE *****************
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//**********************************************************
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//**********************************************************
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//**********************************************************
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// ---------------------------------------------------------
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// ---------------------------------------------------------
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// DO NOT MODIFY ANYTHING BELOW THIS
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// ---------------------------------------------------------
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// ---------------------------------------------------------
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// We are providing this adapter, due to the format of Chisel-generated Verilog
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// and it's compatibility with a blackbox interface.
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//
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// This adapter converts the Gemmini multiplication function into something
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// more amenable to teaching:
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//
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// Assumed that bias matrix is 0.
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//
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// Originally Gemmini does:
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// A*D + B => B
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// 0 => C
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//
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// This adapter converts it to the following:
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// A*B + D => C
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// 0 => B
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module MeshBlackBoxAdapter
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#(parameter MESHROWS, MESHCOLUMNS, INPUT_BITWIDTH, OUTPUT_BITWIDTH, MAX_SIM_MM_LOG, ACC_BITWIDTH_LOG, TILEROWS=1, TILECOLUMNS=1)
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(
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input clock,
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input reset,
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input [MESHROWS*TILEROWS*INPUT_BITWIDTH-1:0] in_a,
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input [MESHCOLUMNS*TILECOLUMNS*INPUT_BITWIDTH-1:0] in_d,
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input [MESHCOLUMNS*TILECOLUMNS*INPUT_BITWIDTH-1:0] in_b,
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input [MESHCOLUMNS*TILECOLUMNS-1:0] in_control_dataflow,
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input [MESHCOLUMNS*TILECOLUMNS-1:0] in_control_propagate,
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input [MESHCOLUMNS*TILECOLUMNS*ACC_BITWIDTH_LOG-1:0] in_control_shift,
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input [MESHCOLUMNS*TILECOLUMNS-1:0] in_valid,
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input [MESHCOLUMNS*TILECOLUMNS*MAX_SIM_MM_LOG-1:0] in_id,
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input [MESHCOLUMNS*TILECOLUMNS-1:0] in_last,
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output [MESHCOLUMNS*TILECOLUMNS*OUTPUT_BITWIDTH-1:0] out_c,
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output [MESHCOLUMNS*TILECOLUMNS*OUTPUT_BITWIDTH-1:0] out_b,
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output [MESHCOLUMNS*TILECOLUMNS-1:0] out_valid,
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output [MESHCOLUMNS*TILECOLUMNS-1:0] out_control_dataflow,
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output [MESHCOLUMNS*TILECOLUMNS-1:0] out_control_propagate,
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output [MESHCOLUMNS*TILECOLUMNS*ACC_BITWIDTH_LOG-1:0] out_control_shift,
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output [MESHCOLUMNS*TILECOLUMNS*MAX_SIM_MM_LOG-1:0] out_id,
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output [MESHCOLUMNS*TILECOLUMNS-1:0] out_last
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);
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wire signed [INPUT_BITWIDTH-1:0] in_a_2d[MESHROWS-1:0][TILEROWS-1:0];
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wire signed [INPUT_BITWIDTH-1:0] in_d_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire signed [INPUT_BITWIDTH-1:0] in_b_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire in_control_dataflow_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire in_control_propagate_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire [ACC_BITWIDTH_LOG-1:0] in_control_shift_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire in_valid_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire [MAX_SIM_MM_LOG-1:0] in_id_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire in_last_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire signed [OUTPUT_BITWIDTH-1:0] out_c_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire signed [OUTPUT_BITWIDTH-1:0] out_b_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire out_valid_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire out_control_dataflow_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire out_control_propagate_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire [ACC_BITWIDTH_LOG-1:0] out_control_shift_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire [MAX_SIM_MM_LOG-1:0] out_id_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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wire out_last_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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reg signed [OUTPUT_BITWIDTH-1:0] reg_out_c_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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reg signed [OUTPUT_BITWIDTH-1:0] reg_out_b_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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reg reg_out_valid_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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reg reg_out_control_dataflow_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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reg reg_out_control_propagate_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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reg [ACC_BITWIDTH_LOG-1:0] reg_out_control_shift_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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reg [MAX_SIM_MM_LOG-1:0] reg_out_id_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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reg reg_out_last_2d[MESHCOLUMNS-1:0][TILECOLUMNS-1:0];
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// Convert wide signals into "cleaner" 2D Verilog arrays
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genvar i;
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genvar j;
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generate
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for (i = 0; i < MESHROWS ; i++) begin
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for (j = 0; j < TILEROWS ; j++) begin
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assign in_a_2d[i][j] = in_a[i*(TILEROWS*INPUT_BITWIDTH)+(j+1)*(INPUT_BITWIDTH)-1:i*(TILEROWS*INPUT_BITWIDTH)+j*(INPUT_BITWIDTH)];
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end
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end
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endgenerate
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generate
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for (i = 0; i < MESHCOLUMNS ; i++) begin
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for (j = 0; j < TILECOLUMNS ; j++) begin
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assign in_d_2d[i][j] = in_d[i*(TILECOLUMNS*INPUT_BITWIDTH)+(j+1)*(INPUT_BITWIDTH)-1:i*(TILECOLUMNS*INPUT_BITWIDTH)+j*(INPUT_BITWIDTH)];
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assign in_b_2d[i][j] = in_b[i*(TILECOLUMNS*INPUT_BITWIDTH)+(j+1)*(INPUT_BITWIDTH)-1:i*(TILECOLUMNS*INPUT_BITWIDTH)+j*(INPUT_BITWIDTH)];
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assign in_control_dataflow_2d[i][j] = in_control_dataflow[i*(TILECOLUMNS)+(j+1)-1:i*(TILECOLUMNS)+j];
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assign in_control_propagate_2d[i][j] = in_control_propagate[i*(TILECOLUMNS)+(j+1)-1:i*(TILECOLUMNS)+j];
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assign in_control_shift_2d[i][j] = in_control_shift[i*(TILECOLUMNS*ACC_BITWIDTH_LOG)+(j+1)*(ACC_BITWIDTH_LOG)-1:i*(TILECOLUMNS*ACC_BITWIDTH_LOG)+j*(ACC_BITWIDTH_LOG)];
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assign in_valid_2d[i][j] = in_valid[i*(TILECOLUMNS)+(j+1)-1:i*(TILECOLUMNS)+j];
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assign in_id_2d[i][j] = in_id[i*(TILECOLUMNS*MAX_SIM_MM_LOG)+(j+1)*(MAX_SIM_MM_LOG)-1:i*(TILECOLUMNS*MAX_SIM_MM_LOG)+j*(MAX_SIM_MM_LOG)];
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assign in_last_2d[i][j] = in_last[i*(TILECOLUMNS)+(j+1)-1:i*(TILECOLUMNS)+j];
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assign out_c[i*(TILECOLUMNS*OUTPUT_BITWIDTH)+(j+1)*(OUTPUT_BITWIDTH)-1:i*(TILECOLUMNS*OUTPUT_BITWIDTH)+j*(OUTPUT_BITWIDTH)] = reg_out_c_2d[i][j];
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assign out_b[i*(TILECOLUMNS*OUTPUT_BITWIDTH)+(j+1)*(OUTPUT_BITWIDTH)-1:i*(TILECOLUMNS*OUTPUT_BITWIDTH)+j*(OUTPUT_BITWIDTH)] = reg_out_b_2d[i][j];
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assign out_valid[i*(TILECOLUMNS)+(j+1)-1:i*(TILECOLUMNS)+j] = reg_out_valid_2d[i][j];
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assign out_control_dataflow[i*(TILECOLUMNS)+(j+1)-1:i*(TILECOLUMNS)+j] = reg_out_control_dataflow_2d[i][j];
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assign out_control_propagate[i*(TILECOLUMNS)+(j+1)-1:i*(TILECOLUMNS)+j] = reg_out_control_propagate_2d[i][j];
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assign out_control_shift[i*(TILECOLUMNS*ACC_BITWIDTH_LOG)+(j+1)*(ACC_BITWIDTH_LOG)-1:i*(TILECOLUMNS*ACC_BITWIDTH_LOG)+j*(ACC_BITWIDTH_LOG)] = reg_out_control_shift_2d[i][j];
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assign out_id[i*(TILECOLUMNS*MAX_SIM_MM_LOG)+(j+1)*(MAX_SIM_MM_LOG)-1:i*(TILECOLUMNS*MAX_SIM_MM_LOG)+j*(MAX_SIM_MM_LOG)] = reg_out_id_2d[i][j];
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assign out_last[i*(TILECOLUMNS)+(j+1)-1:i*(TILECOLUMNS)+j] = reg_out_last_2d[i][j];
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always @(posedge clock) begin
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if (reset) begin
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// reset all values to 0
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reg_out_c_2d[i][j] <= '0;
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reg_out_b_2d[i][j] <= '0;
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reg_out_valid_2d[i][j] <= '0;
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reg_out_control_dataflow_2d[i][j] <= '0;
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reg_out_control_propagate_2d[i][j] <= '0;
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reg_out_control_shift_2d[i][j] <= '0;
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reg_out_id_2d[i][j] <= '0;
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reg_out_last_2d[i][j] <= '0;
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end
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else begin
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// regnext the values
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reg_out_c_2d[i][j] <= out_c_2d[i][j];
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reg_out_b_2d[i][j] <= out_b_2d[i][j];
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reg_out_valid_2d[i][j] <= out_valid_2d[i][j];
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reg_out_control_dataflow_2d[i][j] <= out_control_dataflow_2d[i][j];
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reg_out_control_propagate_2d[i][j] <= out_control_propagate_2d[i][j];
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reg_out_control_shift_2d[i][j] <= out_control_shift_2d[i][j];
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reg_out_id_2d[i][j] <= out_id_2d[i][j];
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reg_out_last_2d[i][j] <= out_last_2d[i][j];
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end
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end
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end
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end
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endgenerate
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// Instantiate the Mesh BlackBox implementation (the one you are writing in
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// this assignment)
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// Note: This swaps signals around a bit:
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// in_b <-> in_d
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// out_c <-> out_b
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MeshBlackBox #(.MESHROWS(MESHROWS),.TILEROWS(TILEROWS),.MESHCOLUMNS(MESHCOLUMNS),.MAX_SIM_MM_LOG(MAX_SIM_MM_LOG),.ACC_BITWIDTH_LOG(ACC_BITWIDTH_LOG), .TILECOLUMNS(TILECOLUMNS),.INPUT_BITWIDTH(INPUT_BITWIDTH),.OUTPUT_BITWIDTH(OUTPUT_BITWIDTH))
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mesh_blackbox_inst (
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.clock (clock),
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.reset (reset),
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.in_a (in_a_2d),
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.in_d (in_b_2d),
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.in_b (in_d_2d),
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.in_control_dataflow (in_control_dataflow_2d),
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.in_control_propagate (in_control_propagate_2d),
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.in_control_shift (in_control_shift_2d),
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.in_valid (in_valid_2d),
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.in_id (in_id_2d),
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.in_last (in_last_2d),
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.out_c (out_b_2d),
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.out_b (out_c_2d),
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.out_valid (out_valid_2d),
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.out_control_dataflow (out_control_dataflow_2d),
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.out_control_propagate (out_control_propagate_2d),
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.out_control_shift (out_control_shift_2d),
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.out_id (out_id_2d),
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.out_last (out_last_2d)
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);
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endmodule //MeshBlackBoxAdapter

‎src/main/scala/gemmini/ConfigsEE290.scala

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package gemmini
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import chisel3._
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import org.chipsalliance.cde.config.{Config, Parameters}
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import freechips.rocketchip.diplomacy.{LazyModule, ValName}
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.tile.{BuildRoCC, OpcodeSet}
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// -----------------------------
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// EE290 Class Config Mixins
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// -----------------------------
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object GemminiEE290Configs{
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import GemminiConfigs.{defaultConfig => base}
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val defaultConfig = base.copy()
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// Change meshRows and meshColumns to change the size of your systolic array
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val lab3Config = defaultConfig.copy(meshRows = 8, meshColumns = 8, dataflow = Dataflow.WS)
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// For Lab3 Part 3.6
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val lab3LargeSPConfig = defaultConfig.copy(meshRows = 8, meshColumns = 8, dataflow = Dataflow.WS, sp_capacity = CapacityInKilobytes(2048))
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}
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//===========EE290 Lab3 Config=========
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class GemminiEE290Lab3Config extends Config((site, here, up) => {
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case BuildRoCC => Seq(
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(p: Parameters) => {
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implicit val q = p
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val gemmini = LazyModule(new Gemmini(GemminiEE290Configs.lab3Config.copy(
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opcodes = OpcodeSet.custom3
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)))
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gemmini
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}
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)
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case SystemBusKey => up(SystemBusKey).copy(beatBytes = 16)
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})
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//===========EE290 Lab3 Large Scratchpad Config=========
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class GemminiEE290Lab3LargeSPConfig extends Config((site, here, up) => {
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case BuildRoCC => Seq(
41+
(p: Parameters) => {
42+
implicit val q = p
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val gemmini = LazyModule(new Gemmini(GemminiEE290Configs.lab3LargeSPConfig.copy(
44+
opcodes = OpcodeSet.custom3
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)))
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gemmini
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}
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)
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case SystemBusKey => up(SystemBusKey).copy(beatBytes = 16)
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})

‎src/main/scala/gemmini/GemminiConfigs.scala

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Original file line numberDiff line numberDiff line change
@@ -228,7 +228,8 @@ case class GemminiArrayConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
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val LOG2_MNK_BYTES = log2Up(MNK_BYTES)
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val MNK_BYTES_PER_TILE_ROW = MNK_BYTES * DIM
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val LOG2_MNK_BYTES_PER_TILE_ROW = log2Up(MNK_BYTES_PER_TILE_ROW)
231-
val TILE_IDX = MNK_BYTES / (DIM / cisc_dim)
231+
val TILE_IDX = (BigInt(MNK_BYTES)*cisc_dim) / (DIM)
232+
//val TILE_IDX = MNK_BYTES / (DIM / cisc_dim)
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val LOG2_TILE_IDX = log2Up(TILE_IDX)
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//--------------------------------------------------------------------------

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