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Amanda ShiAmanda Shi
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add interface between scale factor mem and L1
1 parent 8026a5e commit 50c2a71

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5 files changed

+12
-10
lines changed

5 files changed

+12
-10
lines changed

src/main/scala/gemmini/ConfigsFP.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -273,8 +273,8 @@ object GemminiMxFPConfigs {
273273
Seq.fill(4) {MxFloat(8, 8, 4, true, false)},
274274

275275
// 16x16 mesh with varying precisions
276-
scaleMem_data_width = 128,
277-
scaleMem_bank_entries = 8192,
276+
// scaleMem_data_width = 128,
277+
// scaleMem_write_data_addr_width = 32,
278278
scaleSize = 32,
279279
enable_lut = true,
280280
mvin_scale_args = None,

src/main/scala/gemmini/Controller.scala

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -180,12 +180,12 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
180180
val mx_requantizer = Option.when(outer.config.use_mx_scaling && outer.config.requantizer.isDefined && outer.config.lut.isDefined) {
181181
val q = outer.config.requantizer.get
182182
val l = outer.config.lut.get
183-
183+
184184
Module(new MxRequantizer(
185185
sp_data_width = outer.config.sp_width,
186186
sp_addr_width = log2Ceil(outer.config.sp_bank_entries),
187-
scaleMem_data_width = outer.config.scaleMem_data_width,
188-
scaleMem_addr_width = log2Ceil(outer.config.scaleMem_bank_entries),
187+
scaleMem_data_width = outer.config.scale_mem.get.ScaleMemWriteDataWidth,
188+
scaleMem_addr_width = outer.config.scale_mem.get.ScaleMemWriteAddrWidth,
189189
scaleSize = outer.config.scaleSize,
190190
scaleMembasewrite = 0, // TODO: add this into the instruction
191191
lutConfig = l,
@@ -217,7 +217,7 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
217217
val lut0 = Flipped(Decoupled(new QuantLutWriteBundle(l)))
218218
val lut1 = Flipped(Decoupled(new QuantLutWriteBundle(l)))
219219
val lut2 = Flipped(Decoupled(new QuantLutWriteBundle(l)))
220-
//val scaleFactorOut = Decoupled(new ScalingFactorWriteReq(scaleMem_addr_width, scaleMem_data_width))
220+
//val scaleFactorOut = Decoupled(new ScalingFactorWriteReq(s.ScaleMemWriteAddrWidth, s.ScaleMemWriteAddrWidth))
221221
})
222222

223223

src/main/scala/gemmini/GemminiConfigs.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -56,8 +56,8 @@ case class GemminiArrayConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
5656
acc_latency: Int = 2,
5757

5858

59-
scaleMem_data_width: Int = 128,
60-
scaleMem_bank_entries: Int = 8192,
59+
// scaleMem_write_data_width: Int = 128,
60+
// scaleMem_write_data_addr_width: Int = 32,
6161
scaleSize: Int = 32,
6262

6363
dma_maxbytes: Int = 64, // TODO get this from cacheblockbytes

src/main/scala/gemmini/MxConfigFragments.scala

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,8 @@ case class GemminiScalingFactorMemConfig(
1010
subbanksPerBank: Int = 2,
1111
gpuInputWidthBytes: Int = 8,
1212
numBanks: Int = 8,
13+
ScaleMemWriteDataWidth: Int = 256,
14+
ScaleMemWriteAddrWidth: Int = 32,
1315
) {
1416
def depth: Int = (sizeInBytes / (subbankLineSizeInBytes) / numBanks).toInt
1517
def bankWidthBytes = subbankLineSizeInBytes * subbanksPerBank

src/main/scala/gemmini/MxRequantizer.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -346,11 +346,11 @@ class MxRequantizer[T <: Data: Arithmetic](
346346
scale_buffer_full := true.B
347347
}.otherwise {
348348
scale_write_counter := scale_write_counter + 1.U
349-
when(io.scaleMem_write.ready){
349+
when(io.scaleMem_write.fire){
350350
scale_buffer_full := false.B
351351
}
352352
}
353-
}.elsewhen(io.scaleMem_write.ready){
353+
}.elsewhen(io.scaleMem_write.fire){
354354
scale_buffer_full := false.B
355355
}
356356

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