change the QuantLut as double buffer

Author: Amanda Shi

chipyard/GemminiConfigs.scala

@@ -60,6 +60,6 @@ class TestMxGemminiRocketConfig extends Config(
 
 class TestRequantizerLutMxGemminiRocketConfig extends Config(
   new gemmini.GemminiRequantizerLutMxFPTestConfig ++                         // use FP32Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
-  new chipyard.config.WithSystemBusWidth(128) ++
+  new freechips.rocketchip.rocket.WithNSmallCores(1) ++
+  new chipyard.config.WithSystemBusWidth(256) ++
   new chipyard.config.AbstractConfig)

src/main/scala/gemmini/Controller.scala

@@ -192,6 +192,7 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
       sp_banks = outer.config.sp_banks,
       sp_width = outer.config.sp_width,
       sp_width_projected = outer.config.sp_width_projected,
+      iterator_bitwidth = 16,
       config = q  
     ))
   }
@@ -201,6 +202,7 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
   req.io.fp8_mode := false.B
 }
 
+
   val mx_io = Option.when(outer.config.use_mx_scaling && outer.config.requantizer.isDefined && outer.config.lut.isDefined) {
     val q = outer.config.requantizer.get
     val l = outer.config.lut.get
@@ -213,7 +215,7 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
       val lut2 = Flipped(Decoupled(new QuantLutWriteBundle(l)))
     })
 
-    mx_io.scale_mem <> spad.module.io.scale_mem.get
+    //mx_io.scale_mem <> spad.module.io.scale_mem.get
 
     mx_io.requant_out <> mx_requantizer.get.io.requant_data_out
     mx_requantizer.get.io.lut0_write <> mx_io.lut0
@@ -245,22 +247,27 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
         mx_sel(bank) := (ex_controller.io.output_MxFormat === 1.U)
       }
     }
-    // if(outer.config.lut.isDefined){
-    //   mx_requantizer.get.io.lut_write := DontCare
-    // }
+    if(outer.config.lut.isDefined){
+      mx_requantizer.get.io.lut_write_0 := DontCare
+      mx_requantizer.get.io.lut_write_1 := DontCare
+      mx_requantizer.get.io.lut_write_2 := DontCare
+    }
   }
 
   for (bank <- 0 until sp_banks) {
     val useMxB = mx_requantizer.isDefined.B && mx_sel(bank)
     // Requests
     // default
+
+    
     read_projected(bank).req.valid := sram_read_buffer(bank).req.valid && !useMxB
     read_projected(bank).req.bits := sram_read_buffer(bank).req.bits
     sram_read_buffer(bank).req.ready := Mux(useMxB, mx_requantizer.get.io.spad_projected_data(bank).req.ready, read_projected(bank).req.ready)
     // mx
+
     mx_requantizer.get.io.spad_deprojected_data(bank).req.valid := sram_read_buffer(bank).req.valid && useMxB
     mx_requantizer.get.io.spad_deprojected_data(bank).req.bits := sram_read_buffer(bank).req.bits
-
+   
     // Responses
 
     read_projected(bank).resp.valid := Mux(useMxB, mx_requantizer.get.io.spad_projected_data(bank).resp.valid, sram_read_buffer(bank).resp.valid)
@@ -293,7 +300,7 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
         requantized_writes(i).mask := VecInit(Seq.fill(requantized_writes(i).mask.length)(true.B))
       }
 
-      mx_io.get.requant_in_gpu.ready := false.B
+      //mx_io.get.requant_in_gpu.ready := false.B
       mx_requantizer.get.io.requant_data_in.valid := false.B
       mx_requantizer.get.io.requant_data_in.bits := DontCare
       mx_requantizer.get.io.scaleMem_write.ready := false.B
@@ -326,7 +333,7 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
 
 
       }.elsewhen(any_valid) {
-        mx_io.get.requant_in_gpu.ready := false.B
+        //mx_io.get.requant_in_gpu.ready := false.B
 
         val collected_data = Wire(Vec(outer.config.requantizer.get.numInputLanes, UInt(outer.config.weightType.getWidth.W)))
         collected_data := DontCare
@@ -363,33 +370,33 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
           mx_requantizer.get.io.requant_data_in.bits.dataType := RequantizerDataType.FP8
         }
 
-      }.elsewhen(mx_io.get.requant_in_gpu.valid) {
-      //.elsewhen(!any_valid) {
+      }//.elsewhen(mx_io.get.requant_in_gpu.valid) {
+      .elsewhen(!any_valid) {
 
-        val padded_data = VecInit(mx_io.get.requant_in_gpu.bits.data ++ 
-                              Seq.fill(64 - 16)(0.U(16.W)))
-        mx_requantizer.get.io.requant_data_in.valid := true.B
-        mx_requantizer.get.io.requant_data_in.bits.data := padded_data
-        mx_requantizer.get.io.requant_data_in.bits.address := mx_io.get.requant_in_gpu.bits.address
-        mx_requantizer.get.io.requant_data_in.bits.dataType := mx_io.get.requant_in_gpu.bits.dataType
-        mx_io.get.requant_in_gpu.ready := true.B
-        // val padded_data = VecInit(Seq.fill(64)(0.U(16.W)))
+        // val padded_data = VecInit(mx_io.get.requant_in_gpu.bits.data ++ 
+        //                       Seq.fill(64 - 16)(0.U(16.W)))
         // mx_requantizer.get.io.requant_data_in.valid := true.B
         // mx_requantizer.get.io.requant_data_in.bits.data := padded_data
-        // mx_requantizer.get.io.requant_data_in.bits.address := 0.U
-        // mx_requantizer.get.io.requant_data_in.bits.dataType := RequantizerDataType.FP8
+        // mx_requantizer.get.io.requant_data_in.bits.address := mx_io.get.requant_in_gpu.bits.address
+        // mx_requantizer.get.io.requant_data_in.bits.dataType := mx_io.get.requant_in_gpu.bits.dataType
+        // mx_io.get.requant_in_gpu.ready := true.B
+        val padded_data = VecInit(Seq.fill(64)(0.U(16.W)))
+        mx_requantizer.get.io.requant_data_in.valid := true.B
+        mx_requantizer.get.io.requant_data_in.bits.data := padded_data
+        mx_requantizer.get.io.requant_data_in.bits.address := 0.U
+        mx_requantizer.get.io.requant_data_in.bits.dataType := RequantizerDataType.FP8
 
       }.otherwise {
         mx_requantizer.get.io.requant_data_in.valid := false.B
         mx_requantizer.get.io.requant_data_in.bits := DontCare
-        mx_io.get.requant_in_gpu.ready := false.B
+        //mx_io.get.requant_in_gpu.ready := false.B
       }
 
     }.otherwise {
       // enable_MXQuant == 0
       mx_requantizer.get.io.requant_data_in.valid := false.B
       mx_requantizer.get.io.requant_data_in.bits := DontCare
-      mx_io.get.requant_in_gpu.ready := false.B
+      //mx_io.get.requant_in_gpu.ready := false.B
     }
 
     requantized_writes
@@ -502,12 +509,19 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
     has_training_convs, has_max_pool, has_first_layer_optimizations, has_dw_convs) }
   else (raw_cmd, false.B)
 
-  val (loop_cmd, loop_matmul_unroller_busy, loop_completed) = withClock (gated_clock) { LoopMatmul(if (has_loop_conv) conv_cmd else raw_cmd, reservation_station.io.matmul_ld_completed, reservation_station.io.matmul_st_completed, reservation_station.io.matmul_ex_completed,
+  val (loop_cmd, loop_matmul_unroller_busy, loop_completed, loop_matmul) = withClock (gated_clock) { LoopMatmul(if (has_loop_conv) conv_cmd else raw_cmd, reservation_station.io.matmul_ld_completed, reservation_station.io.matmul_st_completed, reservation_station.io.matmul_ex_completed,
     meshRows*tileRows, coreMaxAddrBits, reservation_station_entries, max_lds, max_exs, max_sts, sp_banks * sp_bank_entries, acc_banks * acc_bank_entries,
     inputType.getWidth, accType.getWidth, dma_maxbytes, new MvinRs2(mvin_rows_bits, mvin_cols_bits, local_addr_t),
     new PreloadRs(mvin_rows_bits, mvin_cols_bits, local_addr_t), new PreloadRs(mvout_rows_bits, mvout_cols_bits, local_addr_t),
     new ComputeRs(mvin_rows_bits, mvin_cols_bits, local_addr_t), new ComputeRs(mvin_rows_bits, mvin_cols_bits, local_addr_t),
     new MvoutSpadRs1(32, local_addr_t), new MvoutRs2(mvout_rows_bits, mvout_cols_bits, local_addr_t)) }
+  
+  mx_requantizer.get.io.counter_i := loop_matmul.io.counter_i
+  mx_requantizer.get.io.counter_j := loop_matmul.io.counter_j  
+  mx_requantizer.get.io.counter_k := loop_matmul.io.counter_k
+  mx_requantizer.get.io.a_fire := ex_controller.io.a_fire
+  mx_requantizer.get.io.b_fire := ex_controller.io.b_fire
+
 
   val unrolled_cmd = Queue(loop_cmd)
   unrolled_cmd.ready := false.B

src/main/scala/gemmini/ExecuteController.scala

@@ -50,6 +50,8 @@ class ExecuteController[T <: Data, U <: Data, V <: Data](xLen: Int, tagWidth: In
     val enable_MXQuant = Output(Bool())
 
     val counter = new CounterEventIO()
+    val b_fire = Output(Bool())
+    val a_fire = Output(Bool())
   })
 
 
@@ -196,7 +198,7 @@ def extractHalf(data: UInt, use_high_half: Bool): UInt = {
   // Dependency stuff
   io.completed.valid := false.B
   io.completed.bits := DontCare
-
+  
   // val pending_completed_rob_id = Reg(UDValid(UInt(log2Up(rob_entries).W)))
   val pending_completed_rob_ids = Reg(Vec(2, UDValid(UInt(log2Up(reservation_station_entries).W))))
 
@@ -499,6 +501,10 @@ def extractHalf(data: UInt, use_high_half: Bool): UInt = {
     io.srams.read(i).resp.ready := false.B
   }
 
+
+  io.a_fire := a_fire
+  io.b_fire := b_fire
+
   // Accumulator read
   for (i <- 0 until acc_banks) {
     val read_a_from_acc = a_valid && a_read_from_acc && dataABankAcc === i.U && start_inputting_a && !multiply_garbage && a_row_is_not_all_zeros && !(im2col_wire&&im2col_en)

src/main/scala/gemmini/LoopMatmul.scala

@@ -906,6 +906,9 @@ class LoopMatmul(block_size: Int, coreMaxAddrBits: Int, reservation_station_size
     val ex_completed = Input(UInt(log2Up(reservation_station_size+1).W))
     val busy = Output(Bool())
     val completed = Output(Vec(2, Bool()))
+    val counter_i = Output(UInt(16.W))
+    val counter_j = Output(UInt(16.W))
+    val counter_k = Output(UInt(16.W))
   })
 
   // Create states
@@ -934,6 +937,9 @@ class LoopMatmul(block_size: Int, coreMaxAddrBits: Int, reservation_station_size
 
   // Create command queue
   val cmd = Queue(io.in)
+  io.counter_i := ex.io.i
+  io.counter_j := ex.io.j
+  io.counter_k := ex.io.k
 
   io.busy := cmd.valid || loop_configured
 
@@ -1306,15 +1312,15 @@ object LoopMatmul {
             max_addr: Int, max_acc_addr: Int, input_w: Int, acc_w: Int, dma_max_bytes: Int,
             mvin_rs2_t: MvinRs2, preload_rs1_t: PreloadRs, preload_rs2_t: PreloadRs,
             compute_rs1_t: ComputeRs, compute_rs2_t: ComputeRs, mvout_spad_rs1_t: MvoutSpadRs1, mvout_rs2_t: MvoutRs2)
-           (implicit p: Parameters): (DecoupledIO[GemminiCmd], Bool, Vec[Bool]) = {
+           (implicit p: Parameters): (DecoupledIO[GemminiCmd], Bool, Vec[Bool], LoopMatmul) = {
     val mod = Module(new LoopMatmul(block_size, coreMaxAddrBits, rob_size, max_lds, max_exs, max_sts,
       max_addr, max_acc_addr, input_w, acc_w, dma_max_bytes,
       mvin_rs2_t, preload_rs1_t, preload_rs2_t, compute_rs1_t, compute_rs2_t, mvout_spad_rs1_t, mvout_rs2_t))
     mod.io.in <> in
     mod.io.ld_completed := ld_completed
     mod.io.st_completed := st_completed
     mod.io.ex_completed := ex_completed
-    (mod.io.out, mod.io.busy, mod.io.completed)
+    (mod.io.out, mod.io.busy, mod.io.completed, mod)
   }
 
   def castDramOffset(dram_offset: UInt): UInt = {

src/main/scala/gemmini/MxConfigFragments.scala

@@ -26,6 +26,9 @@ case class GemminiRequantizerConfig(
   minOutputBits: Int = 4,
   maxOutputBits: Int = 8,
   outputIdBits: Int = 3,
+  lutUpdateRegularityW : Int = 128, 
+  lutUpdateRegularityActIn : Int = 128,
+  lutUpdateRegularityActOut : Int = 128,  
 )
 
 case class GemminiLUTConfig(

src/main/scala/gemmini/MxRequantizer.scala

@@ -49,6 +49,7 @@ class MxRequantizerIO(
   sp_banks: Int,
   sp_width: Int,
   sp_width_projected: Int,
+  iterator_bitwidth: Int,
   config: GemminiRequantizerConfig 
 ) extends Bundle {
   val inputnumLanes = config.numInputLanes
@@ -63,6 +64,11 @@ class MxRequantizerIO(
   val spad_projected_data = Vec(sp_banks, new ScratchpadReadIO(sp_bank_entries, sp_width_projected))
   val spad_deprojected_data = Vec(sp_banks, Flipped(new ScratchpadReadIO(sp_bank_entries, sp_width)))
   val fp8_mode = Input(Bool())  // true for 64-lane mode, false for 16-lane mode
+  val a_fire = Input(Bool())  // from execute controller
+  val b_fire = Input(Bool())  // from execute controller
+  val counter_i = Input(UInt(iterator_bitwidth.W)) // from  controller
+  val counter_j = Input(UInt(iterator_bitwidth.W)) // from  controller
+  val counter_k = Input(UInt(iterator_bitwidth.W)) // from  controller
 }
 
 class MxRequantizer[T <: Data: Arithmetic](
@@ -77,6 +83,7 @@ class MxRequantizer[T <: Data: Arithmetic](
   sp_banks: Int,
   sp_width: Int,
   sp_width_projected: Int,
+  iterator_bitwidth: Int,
   config: GemminiRequantizerConfig 
 )(implicit ev: Arithmetic[T]) extends Module {
 
@@ -94,6 +101,7 @@ class MxRequantizer[T <: Data: Arithmetic](
     sp_banks,
     sp_width,
     sp_width_projected,
+    iterator_bitwidth,
     config
   ))
 
@@ -252,12 +260,19 @@ class MxRequantizer[T <: Data: Arithmetic](
     sp_bank_entries = sp_bank_entries,
     sp_banks = sp_banks,
     sp_width = sp_width,
-    sp_width_projected = sp_width_projected
+    sp_width_projected = sp_width_projected,
+    lut_update_regularity_w = config.lutUpdateRegularityW,
+    lut_update_regularity_act_in = config.lutUpdateRegularityActIn,
+    lut_update_regularity_act_out = config.lutUpdateRegularityActOut,
+    iterator_bitwidth = iterator_bitwidth
   ))
 
   quantLut.io.spad_projected_data <> io.spad_projected_data
   quantLut.io.spad_deprojected_data <> io.spad_deprojected_data
-  
+  quantLut.io.a_fire := io.a_fire
+  quantLut.io.b_fire := io.b_fire
+  quantLut.io.counter_i := io.counter_i
+  quantLut.io.counter_j := io.counter_j
   // quantLut.io.lut_write.valid := false.B
   // quantLut.io.lut_write.bits := DontCare
   quantLut.io.quant_fp6.valid := false.B
@@ -273,15 +288,37 @@ class MxRequantizer[T <: Data: Arithmetic](
   //   quantLut.io.lut_write.ready := false.B
   // }
 
+<<<<<<< HEAD
   quantLut.io.lut_write <> io.lut0_write
   io.lut1_write.ready := false.B
   io.lut2_write.ready := false.B
 
+=======
+  quantLut.io.lut_write_weight <> io.lut_write_0
+  quantLut.io.lut_write_act_in <> io.lut_write_1
+  quantLut.io.lut_write_act_out <> io.lut_write_2
+  val quant_fp6_buffer = RegInit(VecInit(Seq.fill(io.outputnumLanes)(0.U(6.W))))
+  val quant_fp6_hang =  RegInit(false.B)
+>>>>>>> e1e04af (change the QuantLut as double buffer)
   when(quantize_valid && (total_bits_per_element === 6.U)) {
-    quantLut.io.quant_fp6.valid := true.B
-    quantLut.io.quant_fp6.bits := quant_fp6
+    when{quantLut.io.lut_write_act_out.ready}{ //hang here when write is finished
+      for (i <- 0 until io.outputnumLanes) {
+        quant_fp6_buffer(i) := quant_fp6(i)
+      }
+      quantLut.io.quant_fp6.valid := false.B 
+      quant_fp6_hang := true.B
+    }
+    when{!quantLut.io.lut_write_act_out.ready } {
+      when (quant_fp6_hang) {
+        quantLut.io.quant_fp6.valid := true.B 
+        quantLut.io.quant_fp6.bits := quant_fp6_buffer
+        quant_fp6_hang := false.B
+      }.otherwise {
+      quantLut.io.quant_fp6.valid := true.B 
+      quantLut.io.quant_fp6.bits := quant_fp6
+      }
+    }
   }
-  
   when(quantLut.io.projected_data.valid && (total_bits_per_element === 6.U)) {
     io.requant_data_out.valid := true.B
     io.requant_data_out.bits.dataType := quant_dataType