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Merge pull request #361 from ucb-bar/rc-bump
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Rc bump
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SeahK authored Jul 12, 2024
2 parents f72dc8c + 6b8abdf commit c3bf717
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2 changes: 1 addition & 1 deletion CHIPYARD.hash
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@@ -1 +1 @@
b4aae0ddfdc5aaced32e0df90b633eab5b8327ca
d75934b0327e8ba44973769d17794df8c2c8ee8b
2 changes: 1 addition & 1 deletion src/main/scala/gemmini/Configs.scala
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Expand Up @@ -4,7 +4,7 @@ import chisel3._
import org.chipsalliance.cde.config.{Config, Parameters}
import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tile.{BuildRoCC, OpcodeSet, XLen}
import freechips.rocketchip.tile.{BuildRoCC, OpcodeSet}
import freechips.rocketchip.rocket._
import freechips.rocketchip.tile._
import freechips.rocketchip.system._
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2 changes: 1 addition & 1 deletion src/main/scala/gemmini/Controller.scala
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Expand Up @@ -32,7 +32,7 @@ class Gemmini[T <: Data : Arithmetic, U <: Data, V <: Data](val config: GemminiA
System.exit(1)
}

val xLen = p(XLen)
val xLen = p(TileKey).core.xLen
val spad = LazyModule(new Scratchpad(config))

override lazy val module = new GemminiModule(this)
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