remove the half row reading logic from spad

Author: Amanda Shi

src/main/scala/gemmini/Controller.scala

@@ -248,9 +248,9 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data]
       }
     }
     if(outer.config.lut.isDefined){
-      mx_requantizer.get.io.lut_write_0 := DontCare
-      mx_requantizer.get.io.lut_write_1 := DontCare
-      mx_requantizer.get.io.lut_write_2 := DontCare
+      mx_requantizer.get.io.lut0_write := DontCare
+      mx_requantizer.get.io.lut1_write := DontCare
+      mx_requantizer.get.io.lut2_write := DontCare
     }
   }
 

src/main/scala/gemmini/ExecuteController.scala

@@ -55,15 +55,15 @@ class ExecuteController[T <: Data, U <: Data, V <: Data](xLen: Int, tagWidth: In
   })
 
 
-def needsBuffering(mx_format: UInt): Bool = {
-  mx_format === 2.U  // FP8 needs buffering
-}
-
-def extractHalf(data: UInt, use_high_half: Bool): UInt = {
-  Mux(use_high_half, 
-    data(255, 128),  // high 128b
-    data(127, 0))    // low 128b
-}
+// def needsBuffering(mx_format: UInt): Bool = {
+//   mx_format === 2.U  // FP8 needs buffering
+// }
+
+// def extractHalf(data: UInt, use_high_half: Bool): UInt = {
+//   Mux(use_high_half, 
+//     data(255, 128),  // high 128b
+//     data(127, 0))    // low 128b
+// }
 
 
   val block_size = meshRows*tileRows
@@ -307,13 +307,13 @@ def extractHalf(data: UInt, use_high_half: Bool): UInt = {
 
   //MX format related
   //val b_data_buffer = Reg(UInt(sp_width.W))
-  val d_data_buffer = Reg(UInt(sp_width.W))
+  // val d_data_buffer = Reg(UInt(sp_width.W))
 
-  //  buffer valid indicators
-  val d_buffer_valid = RegInit(false.B)
+  // //  buffer valid indicators
+  // val d_buffer_valid = RegInit(false.B)
 
-  // half buffer indicators
-  val d_buffer_half = RegInit(false.B)
+  // // half buffer indicators
+  // val d_buffer_half = RegInit(false.B)
 
 
   // TODO merge these into one enum
@@ -468,9 +468,9 @@ def extractHalf(data: UInt, use_high_half: Bool): UInt = {
     val read_b = b_valid && !b_read_from_acc && dataBbank === i.U && start_inputting_b && !accumulate_zeros && b_row_is_not_all_zeros //&& !im2col_wire
     val read_d = d_valid && !d_read_from_acc && dataDbank === i.U && start_inputting_d && !preload_zeros && d_row_is_not_all_zeros //&& !im2col_wire
 
-    val d_needs_sram_read = read_d && !(needsBuffering(weight_mx_format) && d_buffer_valid && !d_buffer_half)
+    //val d_needs_sram_read = read_d && !(needsBuffering(weight_mx_format) && d_buffer_valid && !d_buffer_half)
 
-    Seq((read_a, a_ready), (read_b, b_ready), (d_needs_sram_read, d_ready)).foreach { case (rd, r) =>
+    Seq((read_a, a_ready), (read_b, b_ready), (read_d, d_ready)).foreach { case (rd, r) =>
       when (rd && !io.srams.read(i).req.ready) {
         r := false.B
       }
@@ -884,17 +884,17 @@ def extractHalf(data: UInt, use_high_half: Bool): UInt = {
     cntl.b_read_from_acc -> accReadValid(cntl.b_bank_acc)
   ))
 
-  //val dataD_valid = cntl.d_garbage || cntl.d_unpadded_cols === 0.U || MuxCase(readValid(cntl.d_bank), Seq(
-  //  cntl.preload_zeros -> false.B,
-  //  cntl.d_read_from_acc -> accReadValid(cntl.d_bank_acc)
-  //))
-
-  val dataD_valid = cntl.d_garbage || cntl.d_unpadded_cols === 0.U || 
-  Mux(needsBuffering(weight_mx_format) && d_buffer_valid,
-    true.B,
-    MuxCase(readValid(cntl.d_bank), Seq(
-      cntl.preload_zeros -> false.B,
-      cntl.d_read_from_acc -> accReadValid(cntl.d_bank_acc))))
+  val dataD_valid = cntl.d_garbage || cntl.d_unpadded_cols === 0.U || MuxCase(readValid(cntl.d_bank), Seq(
+   cntl.preload_zeros -> false.B,
+   cntl.d_read_from_acc -> accReadValid(cntl.d_bank_acc)
+  ))
+
+  // val dataD_valid = cntl.d_garbage || cntl.d_unpadded_cols === 0.U || 
+  // Mux(needsBuffering(weight_mx_format) && d_buffer_valid,
+  //   true.B,
+  //   MuxCase(readValid(cntl.d_bank), Seq(
+  //     cntl.preload_zeros -> false.B,
+  //     cntl.d_read_from_acc -> accReadValid(cntl.d_bank_acc))))
 
   //added for negative bitshift
   val preload_zero_counter = RegInit(0.U(5.W))
@@ -904,11 +904,11 @@ def extractHalf(data: UInt, use_high_half: Bool): UInt = {
   val dataA_unpadded = Mux(cntl.im2colling, im2ColData, Mux(cntl.a_read_from_acc, accReadData(cntl.a_bank_acc), readData(cntl.a_bank)))
   val dataB_unpadded = MuxCase(readData(cntl.b_bank), Seq(cntl.accumulate_zeros -> 0.U, cntl.b_read_from_acc -> accReadData(cntl.b_bank_acc)))
 
-  val dataD_from_sram = MuxCase(readData(cntl.d_bank), Seq(cntl.preload_zeros -> 0.U, cntl.d_read_from_acc -> accReadData(cntl.d_bank_acc)))
+  // val dataD_from_sram = MuxCase(readData(cntl.d_bank), Seq(cntl.preload_zeros -> 0.U, cntl.d_read_from_acc -> accReadData(cntl.d_bank_acc)))
 
-  val dataD_unpadded = Mux(needsBuffering(weight_mx_format) && d_buffer_valid, extractHalf(d_data_buffer, d_buffer_half), dataD_from_sram)
+  // val dataD_unpadded = Mux(needsBuffering(weight_mx_format) && d_buffer_valid, extractHalf(d_data_buffer, d_buffer_half), dataD_from_sram)
 
-  //val dataD_unpadded = MuxCase(readData(cntl.d_bank), Seq(cntl.preload_zeros -> 0.U, cntl.d_read_from_acc -> accReadData(cntl.d_bank_acc)))
+  val dataD_unpadded = MuxCase(readData(cntl.d_bank), Seq(cntl.preload_zeros -> 0.U, cntl.d_read_from_acc -> accReadData(cntl.d_bank_acc)))
 
   val dataA = VecInit(dataA_unpadded.asTypeOf(Vec(block_size, inputType)).zipWithIndex.map { case (d, i) => Mux(i.U < cntl.a_unpadded_cols, d, inputType.zero)}.map(d => d.asTypeOf(inputType).withWidthOf(spatialArrayInputType)))
   val dataB = VecInit(dataB_unpadded.asTypeOf(Vec(block_size, accType)).zipWithIndex.map { case (d, i) => Mux(i.U < cntl.b_unpadded_cols, d, accType.zero)}.map(d => d.asTypeOf(accType).withWidthOf(spatialArrayOutputType)))
@@ -933,25 +933,12 @@ def extractHalf(data: UInt, use_high_half: Bool): UInt = {
     }
 
     when (cntl.d_fire && mesh.io.d.fire && !cntl.d_garbage && !cntl.preload_zeros && cntl.d_unpadded_cols > 0.U) {
-      when (needsBuffering(weight_mx_format)) {
-        when (!d_buffer_valid) {
-          when (!cntl.d_read_from_acc && readValid(cntl.d_bank)) {
-            d_data_buffer := readData(cntl.d_bank)
-            d_buffer_valid := true.B
-            d_buffer_half := false.B
-          }
-        }.elsewhen (!d_buffer_half) {
-          d_buffer_half := true.B
-        }.otherwise {
-          d_buffer_valid := false.B
-          d_buffer_half := false.B
-        }
+      when (cntl.d_read_from_acc) {
+        io.acc.read_resp(cntl.d_bank_acc).ready := !io.acc.read_resp(cntl.d_bank_acc).bits.fromDMA
+      }.otherwise {
+        io.srams.read(cntl.d_bank).resp.ready := !io.srams.read(cntl.d_bank).resp.bits.fromDMA
       }
     }
-    when (!firing) {
-      d_buffer_valid := false.B
-      d_buffer_half := false.B
-    }
   }
 
   if (!ex_read_from_acc) {
@@ -960,6 +947,7 @@ def extractHalf(data: UInt, use_high_half: Bool): UInt = {
     }
   }
 
+
   when (cntl_valid) {
     // Default inputs
     mesh.io.a.valid := cntl.a_fire && dataA_valid

src/main/scala/gemmini/MxRequantizer.scala

@@ -288,18 +288,11 @@ class MxRequantizer[T <: Data: Arithmetic](
   //   quantLut.io.lut_write.ready := false.B
   // }
 
-<<<<<<< HEAD
-  quantLut.io.lut_write <> io.lut0_write
-  io.lut1_write.ready := false.B
-  io.lut2_write.ready := false.B
-
-=======
-  quantLut.io.lut_write_weight <> io.lut_write_0
-  quantLut.io.lut_write_act_in <> io.lut_write_1
-  quantLut.io.lut_write_act_out <> io.lut_write_2
+  quantLut.io.lut_write_weight <> io.lut0_write
+  quantLut.io.lut_write_act_in <> io.lut1_write
+  quantLut.io.lut_write_act_out <> io.lut2_write
   val quant_fp6_buffer = RegInit(VecInit(Seq.fill(io.outputnumLanes)(0.U(6.W))))
   val quant_fp6_hang =  RegInit(false.B)
->>>>>>> e1e04af (change the QuantLut as double buffer)
   when(quantize_valid && (total_bits_per_element === 6.U)) {
     when{quantLut.io.lut_write_act_out.ready}{ //hang here when write is finished
       for (i <- 0 until io.outputnumLanes) {

src/main/scala/gemmini/QuantLut.scala

@@ -16,20 +16,11 @@ class QuantLutIO(
   sp_width_projected: Int,
   iterator_bitwidth: Int,
 ) extends Bundle {
-<<<<<<< HEAD
-  val lutReadEnable = Output(Bool()) 
-  val lut_write =  Flipped(Decoupled(new QuantLutWriteBundle(lutConfig))) //input
-  val quant_fp6 = Flipped(Valid(Vec(outputnumLanes, UInt(lutConfig.rdataWidth.W)))) //input
-  val projected_data = Valid(Vec(outputnumLanes, UInt(lutConfig.raddrWidth.W))) //output
-  // val spad_projected_data = Flipped(Decoupled(Vec(sp_banks, new ScratchpadReadIO(sp_bank_entries, sp_width_projected)))) 
-  // val spad_deprojected_data = Decoupled(Vec(sp_banks, new ScratchpadReadIO(sp_bank_entries, sp_width)))
-=======
   val lut_write_weight =  Flipped(Decoupled(new QuantLutWriteBundle(lutConfig))) //input
   val lut_write_act_in =  Flipped(Decoupled(new QuantLutWriteBundle(lutConfig))) //input
   val lut_write_act_out =  Flipped(Decoupled(new QuantLutWriteBundle(lutConfig))) //input
   val quant_fp6 = Flipped(Valid(Vec(outputnumLanes, UInt(lutConfig.rdataWidth.W)))) //input
   val projected_data = Valid(Vec(outputnumLanes, UInt(lutConfig.raddrWidth.W))) //output
->>>>>>> e1e04af (change the QuantLut as double buffer)
   val spad_projected_data   = Vec(sp_banks, new ScratchpadReadIO(sp_bank_entries, sp_width_projected))
   val spad_deprojected_data = Vec(sp_banks, Flipped(new ScratchpadReadIO(sp_bank_entries, sp_width)))
   val counter_j = Input(UInt(iterator_bitwidth.W))
@@ -159,7 +150,6 @@ class QuantLut(
   val lutCache_act_out_buffer_0_read_enable = RegInit(false.B)
   val lutCache_act_out_buffer_1_read_enable = RegInit(false.B)
   val lutCache_act_out_buffer_select = RegInit(false.B)
-  val counter_k_reg = RegNext(io.counter_k)
 
   when(io.lut_write_act_out.fire){
     when(lutCache_act_out_flag === false.B){