CRC Generation Module #54
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rahulk29
requested review from
ansaschmulbach,
ethanwu10,
rahulk29 and
rohanku
| val crc1 = RegInit(Bits(8.W), 0.U) | ||
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| // Output signal registers | ||
| val message_ready = RegInit(Bool(), true.B) |
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I think I was told to use snake case by @rahulk29, but I can switch it to camelcase if that is recommended.
| * and crc valid state low. CRC bits will be cleared to 0. | ||
| * @group Signals | ||
| */ | ||
| val reset = Input(Bool()) |
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use implicit reset instead
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Would I just be able to omit the reset declaration in the IO. I also changed it so that when a new message is latched, the crc output is cleared and set invalid, let me know if this is correct though.
ethanwu10
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ethanwu10
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In terms of architecture, we will probably need something that can run faster than one byte per cycle in order to keep up with the link's speed, and also it might be good to eventually have some sort of streaming capability so that we can feed the module bytes as soon as they are available, instead of collecting the entire word and summing it at once. This is fine for now though and we should probably wait until we better understand how the module will get used to determine what architecture changes to make.
| crc1 := crc0 ^ lookup | ||
| .table(crc1 ^ message_bits(width - 1, width - 8))(15, 8) | ||
| crc0 := lookup.table(crc1 ^ message_bits(width - 1, width - 8))(7, 0) | ||
| message_bits := message_bits << 8 |
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Is this endianness correct? This implementation treats message as one big-endian integer and CRC's bytes from most-significant-byte to LSB (as documented); not sure if this is what we want though.
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Yeah, it's a little unconventional compared to what I normally see for CRC calculations, but the results of this CRC generator match the results of the design the UCIe1.0 spec has in the appendix (where they just selectively xor the 1024 bits of the message for each of the 16 crc bits). I ran a simulation of the xor'ing method in python to generate the test cases I listed in the test module.
Since hardware types can only be instantiated inside of a module, the `table` member is made into a parentheses-less method so that the `VecInit` is constructed at the use site.
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