This is a softcore CPU project I'm doing after realizing that my first one was...more than a little too ambitious for what I am capable of.
The CPU will be a pipelined 16-bit core, with a 16-bit address space, and 16 registers.
The goal is to be able to run the original Final Fantasy on the core. How I'll achieve that, I have yet to figure out. Stay tuned.
Also, a huge shoutout to LordDeCapo and the LTDS server for helping me throughout the course of my journey of learning SystemVerilog. I would highly recommend all who encounter this project to check out his ProcessORC CPU, as well as Slicudis' SRM and martandrMC's PHINIX+.