fix comments

vlib/v/gen/native/amd64.v

@@ -560,7 +560,7 @@ fn (mut c Amd64) mov64u(reg Register, val u64) {
 			c.g.write8(0xbf)
 		}
 		else {
-			eprintln('unhandled mov64 ${reg}')
+			eprintln('unhandled mov64u ${reg}')
 		}
 	}
 	c.g.write64(val)
@@ -569,11 +569,12 @@ fn (mut c Amd64) mov64u(reg Register, val u64) {
 
 fn (mut c Amd64) mov64(reg Register, val i64) {
 	// see AMD64 Architecture Programmer's Manual Volume 3 about the MOV instruction to have a detailed explaination
-	// if you wonder about the BF (B8+rq) there is an explaination about that in Table 2-2 (and a bit above in 2.5.2 Opcode Syntax)
+	// about the BF (B8+rq) there is an explaination in Table 2-2 (and a bit above in 2.5.2 Opcode Syntax)
 	// in short the 64 mov instruction is 0xB8 and after a 64 bits immediate value
 	// but for the cpu to know which register to move the value to, it adds a number to B8
 	// that number is the Value column in table 2-2
 	// for example the bytecode for mov rdx is 0xB8 + 2 so 0xBA
+	// 0x48 is the opcode for REX.W prefix for 64 bits MOV instruction
 	match reg as Amd64Register {
 		.rax {
 			c.g.write8(0x48)

vlib/v/gen/native/expr.v

@@ -62,7 +62,7 @@ fn (mut g Gen) expr(node ast.Expr) {
 			g.code_gen.infix_expr(node)
 		}
 		ast.IntegerLiteral {
-			// Integer literal stores both signed and unsigned integers but sometimes unsigned integers are too big for i64 but not for u64
+			// Integer literal stores both signed and unsigned integers, some unsigned integers are too big for i64 but not for u64
 			println(node.val)
 			if node.val[0] == `-` { // if the number is negative
 				g.code_gen.mov64(g.code_gen.main_reg(), node.val.i64())