[aes,dv] Add AES-GCM to UVM TB #242
Triggered via pull request
February 7, 2025 07:58
nasahlpa
Status
Cancelled
Total duration
3h 13m 17s
Artifacts
3
ci.yml
on: pull_request
Lint (quick)
3m 2s
Lint (slow)
15m 25s
Airgapped build
3m 54s
Verible lint
1m 3s
Verilated English Breakfast
9m 4s
CW305's Bitstream
0s
Build Docker Containers
3m 14s
Annotations
8 errors and 3 warnings
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Verible lint
Process completed with exit code 1.
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Airgapped build
Process completed with exit code 7.
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Lint (slow)
Countermeasure check failed.
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Lint (slow)
Process completed with exit code 1.
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Lint (slow)
Process completed with exit code 1.
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Lint (slow)
Countermeasure check failed.
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Lint (slow)
Process completed with exit code 1.
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CW305's Bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/19/merge' exists
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Verible lint:
hw/ip/aes/dv/env/aes_seq_item.sv#L257
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]" location:{path:"./hw/ip/aes/dv/env/aes_seq_item.sv" range:{start:{line:257 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Verible lint:
hw/ip/aes/dv/env/aes_message_item.sv#L288
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]" location:{path:"./hw/ip/aes/dv/env/aes_message_item.sv" range:{start:{line:288 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Verible lint:
hw/ip/aes/dv/env/aes_scoreboard.sv#L436
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]" location:{path:"./hw/ip/aes/dv/env/aes_scoreboard.sv" range:{start:{line:436 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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Artifacts
Produced during runtime
| Name | Size | |
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verilated_englishbreakfast
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6.67 MB |
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vogelpi~opentitan~B2F22C.dockerbuild
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18.7 KB |
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vogelpi~opentitan~Y5QTTD.dockerbuild
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96.2 KB |
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