Merge remote-tracking branch 'origin/main' into vector_add_transfer_r…

…ead_transfer_write_ops
watermelonwolverine · Jan 2, 2025 · 0ff1569 · 0ff1569
2 parents a702250 + 346e1d4
commit 0ff1569
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diff --git a/.github/workflows/remake-lockfile.yml b/.github/workflows/remake-lockfile.yml
@@ -0,0 +1,39 @@
+name: Remake UV Lockfile
+
+on:
+  workflow_dispatch:
+  # Set the schedule, every week at 8:00am on Monday
+  schedule:
+    - cron: 0 8 * * 1
+
+permissions:
+  contents: write
+  pull-requests: write
+
+jobs:
+  lock:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+
+      - uses: astral-sh/setup-uv@v3
+
+      - run: |
+          rm uv.lock
+          echo "\`\`\`" > uv_output.md
+          make venv &>> uv_output.md
+          echo "\`\`\`" >> uv_output.md
+
+      - name: Create pull request
+        uses: peter-evans/create-pull-request@v7
+        with:
+          token: ${{ secrets.GITHUB_TOKEN }}
+          commit-message: "CI: Update uv lockfile"
+          title: "CI: Update uv lockfile"
+          body-path: uv_output.md
+          branch: ci/update-uv
+          base: main
+          labels: CI
+          delete-branch: true
+          add-paths: uv.lock
+          assignees: math-fehr, georgebisbas, superlopuh
diff --git a/Makefile b/Makefile
@@ -29,6 +29,9 @@ uv-installed:
 .PHONY: ${VENV_DIR}/
 ${VENV_DIR}/: uv-installed
 	XDSL_VERSION_OVERRIDE="0+dynamic" uv sync ${VENV_EXTRAS}
+	@if [ ! -z "$(XDSL_MLIR_OPT_PATH)" ]; then \
+		ln -sf $(XDSL_MLIR_OPT_PATH) ${VENV_DIR}/bin/mlir-opt; \
+	fi
 
 # make sure `make venv` also works correctly
 .PHONY: venv

diff --git a/README.md b/README.md
@@ -101,6 +101,12 @@ cd xdsl
 make venv
 ```
 
+To make a custom mlir-opt available in the virtual environment, set the `XDSL_MLIR_OPT_PATH` variable when running `make venv`, like so:
+
+``` bash
+XDSL_MLIR_OPT_PATH=/PATH/TO/LLVM/BUILD/bin/mlir-opt make venv
+```
+
 #### If you can't use `uv`
 
 For some systems and workflows, changing to a new dependency management system

diff --git a/pyproject.toml b/pyproject.toml
@@ -26,16 +26,16 @@ dev = [
     "lit<19.0.0",
     "marimo==0.9.34",
     "pre-commit==4.0.1",
-    "ruff==0.8.3",
+    "ruff==0.8.4",
     "asv<0.7",
     "nbconvert>=7.7.2,<8.0.0",
     "textual-dev==1.7.0",
-    "pytest-asyncio==0.24.0",
-    "pyright==1.1.390",
+    "pytest-asyncio==0.25.0",
+    "pyright==1.1.391",
 ]
 gui = ["textual==1.0.0", "pyclip==0.7"]
-jax = ["jax==0.4.37", "numpy==2.2.0"]
-onnx = ["onnx==1.17.0", "numpy==2.2.0"]
+jax = ["jax==0.4.38", "numpy==2.2.1"]
+onnx = ["onnx==1.17.0", "numpy==2.2.1"]
 riscv = ["riscemu==2.2.7"]
 wgpu = ["wgpu==0.19.3"]
 

diff --git a/tests/filecheck/backend/csl/print_csl.mlir b/tests/filecheck/backend/csl/print_csl.mlir
@@ -413,7 +413,7 @@ csl.func @builtins() {
   %u32_pointer = "csl.addressof"(%u32_value) : (ui32) -> !csl.ptr<ui32, #csl<ptr_kind single>, #csl<ptr_const var>>
 
   %A = memref.get_global @A : memref<24xf32>
-  %dsd_2d = "csl.get_mem_dsd"(%A, %i32_value, %i32_value) <{"strides" = [3, 4], "offsets" = [1, 2]}> : (memref<24xf32>, si32, si32) -> !csl<dsd mem4d_dsd>
+  %dsd_2d = "csl.get_mem_dsd"(%A, %i32_value, %i32_value) <{"tensor_access" = affine_map<(d0, d1) -> (((d0 * 3) + 1), ((d1 * 4) + 2))>}> : (memref<24xf32>, si32, si32) -> !csl<dsd mem4d_dsd>
   %dest_dsd = "csl.get_mem_dsd"(%A, %i32_value) : (memref<24xf32>, si32) -> !csl<dsd mem1d_dsd>
   %src_dsd1 = "csl.get_mem_dsd"(%A, %i32_value) : (memref<24xf32>, si32) -> !csl<dsd mem1d_dsd>
   %src_dsd2 = "csl.get_mem_dsd"(%A, %i32_value) : (memref<24xf32>, si32) -> !csl<dsd mem1d_dsd>
@@ -426,7 +426,9 @@ csl.func @builtins() {
   %fabin_dsd = "csl.get_fab_dsd"(%i32_value) <{"fabric_color" = 2 : ui5 , "queue_id" = 0 : i3}> : (si32) -> !csl<dsd fabin_dsd>
   %fabout_dsd = "csl.get_fab_dsd"(%i32_value) <{"fabric_color" = 3 : ui5 , "queue_id" = 1 : i3, "control"= true, "wavelet_index_offset" = false}>: (si32) -> !csl<dsd fabout_dsd>
 
-  %zero_stride_dsd = "csl.get_mem_dsd"(%A, %i16_value, %i16_value, %i16_value) <{"strides" = [0 : si16, 0 : si16, 1 : si16]}> : (memref<24xf32>, si16, si16, si16) -> !csl<dsd mem4d_dsd>
+  %zero_stride_dsd = "csl.get_mem_dsd"(%A, %i16_value, %i16_value, %i16_value) <{"tensor_access" = affine_map<(d0, d1, d2) -> (d2)>}> : (memref<24xf32>, si16, si16, si16) -> !csl<dsd mem4d_dsd>
+  %B = memref.get_global @B : memref<3x64xf32>
+  %oned_access_into_twod = "csl.get_mem_dsd"(%B, %i16_value) <{"tensor_access" = affine_map<(d0) -> (1, d0)>}> : (memref<3x64xf32>, si16) -> !csl<dsd mem1d_dsd>
 
   "csl.add16"(%dest_dsd, %src_dsd1,  %src_dsd2)  : (!csl<dsd mem1d_dsd>, !csl<dsd mem1d_dsd>, !csl<dsd mem1d_dsd>) -> ()
   "csl.addc16"(%dest_dsd, %i16_value, %src_dsd1)  : (!csl<dsd mem1d_dsd>, si16, !csl<dsd mem1d_dsd>) -> ()
@@ -795,7 +797,7 @@ csl.func @builtins() {
 // CHECK-NEXT:   var u16_pointer : *u16 = &u16_value;
 // CHECK-NEXT:   var u32_pointer : *u32 = &u32_value;
 // CHECK-NEXT:   const dsd_2d : mem4d_dsd = @get_dsd( mem4d_dsd, .{
-// CHECK-NEXT:     .tensor_access = | d0, d1 | { i32_value, i32_value } -> A[ 3 * d0 + 1, 4 * d1 + 2 ]
+// CHECK-NEXT:     .tensor_access = | d0, d1 | { i32_value, i32_value } -> A[ ((d0 * 3) + 1), ((d1 * 4) + 2) ]
 // CHECK-NEXT:   });
 // CHECK-NEXT:   const dest_dsd : mem1d_dsd = @get_dsd( mem1d_dsd, .{
 // CHECK-NEXT:     .tensor_access = | d0 | { i32_value } -> A[ d0 ]
@@ -825,6 +827,9 @@ csl.func @builtins() {
 // CHECK-NEXT:   const zero_stride_dsd : mem4d_dsd = @get_dsd( mem4d_dsd, .{
 // CHECK-NEXT:     .tensor_access = | d0, d1, d2 | { i16_value, i16_value, i16_value } -> A[ d2 ]
 // CHECK-NEXT:   });
+// CHECK-NEXT:   const oned_access_into_twod : mem1d_dsd = @get_dsd( mem1d_dsd, .{
+// CHECK-NEXT:     .tensor_access = | d0 | { i16_value } -> B[ 1, d0 ]
+// CHECK-NEXT:   });
 // CHECK-NEXT:   @add16(dest_dsd, src_dsd1, src_dsd2);
 // CHECK-NEXT:   @addc16(dest_dsd, i16_value, src_dsd1);
 // CHECK-NEXT:   @and16(dest_dsd, u16_value, src_dsd1);

diff --git a/tests/filecheck/dialects/builtin/module.mlir b/tests/filecheck/dialects/builtin/module.mlir
@@ -1,4 +1,5 @@
 // RUN: XDSL_ROUNDTRIP
+// RUN: xdsl-opt %s --allow-unregistered-dialect | filecheck %s
 
 builtin.module {
   // CHECK: builtin.module {
@@ -8,5 +9,14 @@ builtin.module {
     builtin.module attributes {a = "foo", b = "bar", unit} {}
     // CHECK-NEXT: builtin.module attributes {"a" = "foo", "b" = "bar", "unit"} {
     // CHECK-NEXT: }
+    builtin.module @moduleName {}
+    // CHECK-NEXT: builtin.module @moduleName {
+    // CHECK-NEXT: }
+    builtin.module @otherModule attributes {dialect.attr} {}
+    // CHECK-NEXT: builtin.module @otherModule attributes  {"dialect.attr"} {
+    // CHECK-NEXT: }
+    module {}
+    // CHECK-NEXT: builtin.module {
+    // CHECK-NEXT: }
 }
 // CHECK: }
diff --git a/tests/filecheck/dialects/csl/csl-canonicalize.mlir b/tests/filecheck/dialects/csl/csl-canonicalize.mlir
@@ -8,20 +8,20 @@ builtin.module {
 %1 = "csl.zeros"() : () -> memref<512xf32>
 %2 = "csl.get_mem_dsd"(%1, %0) : (memref<512xf32>, i16) -> !csl<dsd mem1d_dsd>
 
-%3 = arith.constant 1 : si16
-%4 = "csl.increment_dsd_offset"(%2, %3) <{"elem_type" = f32}> : (!csl<dsd mem1d_dsd>, si16) -> !csl<dsd mem1d_dsd>
+%int8 = arith.constant 3 : si8
+%3 = "csl.set_dsd_stride"(%2, %int8) : (!csl<dsd mem1d_dsd>, si8) -> !csl<dsd mem1d_dsd>
 
-%5 = arith.constant 510 : ui16
-%6 = "csl.set_dsd_length"(%4, %5) : (!csl<dsd mem1d_dsd>, ui16) -> !csl<dsd mem1d_dsd>
+%4 = arith.constant 1 : si16
+%5 = "csl.increment_dsd_offset"(%3, %4) <{"elem_type" = f32}> : (!csl<dsd mem1d_dsd>, si16) -> !csl<dsd mem1d_dsd>
 
-%int8 = arith.constant 1 : si8
-%7 = "csl.set_dsd_stride"(%6, %int8) : (!csl<dsd mem1d_dsd>, si8) -> !csl<dsd mem1d_dsd>
+%6 = arith.constant 510 : ui16
+%7 = "csl.set_dsd_length"(%5, %6) : (!csl<dsd mem1d_dsd>, ui16) -> !csl<dsd mem1d_dsd>
 
 "test.op"(%7) : (!csl<dsd mem1d_dsd>) -> ()
 
 // CHECK-NEXT:  %0 = "csl.zeros"() : () -> memref<512xf32>
 // CHECK-NEXT:  %1 = arith.constant 510 : ui16
-// CHECK-NEXT:  %2 = "csl.get_mem_dsd"(%0, %1) <{"offsets" = [1 : si16], "strides" = [1 : si8]}> : (memref<512xf32>, ui16) -> !csl<dsd mem1d_dsd>
+// CHECK-NEXT:  %2 = "csl.get_mem_dsd"(%0, %1) <{"tensor_access" = affine_map<(d0) -> (((d0 * 3) + 1))>}> : (memref<512xf32>, ui16) -> !csl<dsd mem1d_dsd>
 // CHECK-NEXT:  "test.op"(%2) : (!csl<dsd mem1d_dsd>) -> ()
 
 

diff --git a/tests/filecheck/dialects/csl/ops.mlir b/tests/filecheck/dialects/csl/ops.mlir
@@ -89,7 +89,7 @@ csl.func @initialize() {
     %dir = "csl.get_dir"() <{"dir" = #csl<dir_kind north>}> : () -> !csl.direction
 
     %dsd_1d = "csl.get_mem_dsd"(%arr, %scalar) : (memref<10xf32>, i32) -> !csl<dsd mem1d_dsd>
-    %dsd_2d = "csl.get_mem_dsd"(%arr, %scalar, %scalar) <{"strides" = [3, 4], "offsets" = [1, 2]}> : (memref<10xf32>, i32, i32) -> !csl<dsd mem4d_dsd>
+    %dsd_2d = "csl.get_mem_dsd"(%arr, %scalar, %scalar) <{"tensor_access" = affine_map<(d0, d1) -> (((d0 * 3) + 1), ((d1 * 4) + 2))>}> : (memref<10xf32>, i32, i32) -> !csl<dsd mem4d_dsd>
     %dsd_3d = "csl.get_mem_dsd"(%arr, %scalar, %scalar, %scalar) : (memref<10xf32>, i32, i32, i32) -> !csl<dsd mem4d_dsd>
     %dsd_4d = "csl.get_mem_dsd"(%arr, %scalar, %scalar, %scalar, %scalar) : (memref<10xf32>, i32, i32, i32, i32) -> !csl<dsd mem4d_dsd>
     %dsd_1d1 = "csl.set_dsd_base_addr"(%dsd_1d, %many_arr_ptr) : (!csl<dsd mem1d_dsd>, !csl.ptr<f32, #csl<ptr_kind many>, #csl<ptr_const const>>) -> !csl<dsd mem1d_dsd>
@@ -392,7 +392,7 @@ csl.func @builtins() {
 // CHECK-NEXT:       %function_ptr = "csl.addressof_fn"() <{"fn_name" = @initialize}> : () -> !csl.ptr<() -> (), #csl<ptr_kind single>, #csl<ptr_const const>>
 // CHECK-NEXT:       %dir = "csl.get_dir"() <{"dir" = #csl<dir_kind north>}> : () -> !csl.direction
 // CHECK-NEXT:       %dsd_1d = "csl.get_mem_dsd"(%arr, %scalar) : (memref<10xf32>, i32) -> !csl<dsd mem1d_dsd>
-// CHECK-NEXT:       %dsd_2d = "csl.get_mem_dsd"(%arr, %scalar, %scalar) <{"strides" = [3 : i64, 4 : i64], "offsets" = [1 : i64, 2 : i64]}> : (memref<10xf32>, i32, i32) -> !csl<dsd mem4d_dsd>
+// CHECK-NEXT:       %dsd_2d = "csl.get_mem_dsd"(%arr, %scalar, %scalar) <{"tensor_access" = affine_map<(d0, d1) -> (((d0 * 3) + 1), ((d1 * 4) + 2))>}> : (memref<10xf32>, i32, i32) -> !csl<dsd mem4d_dsd>
 // CHECK-NEXT:       %dsd_3d = "csl.get_mem_dsd"(%arr, %scalar, %scalar, %scalar) : (memref<10xf32>, i32, i32, i32) -> !csl<dsd mem4d_dsd>
 // CHECK-NEXT:       %dsd_4d = "csl.get_mem_dsd"(%arr, %scalar, %scalar, %scalar, %scalar) : (memref<10xf32>, i32, i32, i32, i32) -> !csl<dsd mem4d_dsd>
 // CHECK-NEXT:       %dsd_1d1 = "csl.set_dsd_base_addr"(%dsd_1d, %many_arr_ptr) : (!csl<dsd mem1d_dsd>, !csl.ptr<f32, #csl<ptr_kind many>, #csl<ptr_const const>>) -> !csl<dsd mem1d_dsd>
@@ -639,7 +639,7 @@ csl.func @builtins() {
 // CHECK-GENERIC-NEXT:       %function_ptr = "csl.addressof_fn"() <{"fn_name" = @initialize}> : () -> !csl.ptr<() -> (), #csl<ptr_kind single>, #csl<ptr_const const>>
 // CHECK-GENERIC-NEXT:       %dir = "csl.get_dir"() <{"dir" = #csl<dir_kind north>}> : () -> !csl.direction
 // CHECK-GENERIC-NEXT:       %dsd_1d = "csl.get_mem_dsd"(%arr, %scalar) : (memref<10xf32>, i32) -> !csl<dsd mem1d_dsd>
-// CHECK-GENERIC-NEXT:       %dsd_2d = "csl.get_mem_dsd"(%arr, %scalar, %scalar) <{"strides" = [3 : i64, 4 : i64], "offsets" = [1 : i64, 2 : i64]}> : (memref<10xf32>, i32, i32) -> !csl<dsd mem4d_dsd>
+// CHECK-GENERIC-NEXT:       %dsd_2d = "csl.get_mem_dsd"(%arr, %scalar, %scalar) <{"tensor_access" = affine_map<(d0, d1) -> (((d0 * 3) + 1), ((d1 * 4) + 2))>}> : (memref<10xf32>, i32, i32) -> !csl<dsd mem4d_dsd>
 // CHECK-GENERIC-NEXT:       %dsd_3d = "csl.get_mem_dsd"(%arr, %scalar, %scalar, %scalar) : (memref<10xf32>, i32, i32, i32) -> !csl<dsd mem4d_dsd>
 // CHECK-GENERIC-NEXT:       %dsd_4d = "csl.get_mem_dsd"(%arr, %scalar, %scalar, %scalar, %scalar) : (memref<10xf32>, i32, i32, i32, i32) -> !csl<dsd mem4d_dsd>
 // CHECK-GENERIC-NEXT:       %dsd_1d1 = "csl.set_dsd_base_addr"(%dsd_1d, %many_arr_ptr) : (!csl<dsd mem1d_dsd>, !csl.ptr<f32, #csl<ptr_kind many>, #csl<ptr_const const>>) -> !csl<dsd mem1d_dsd>

diff --git a/tests/filecheck/dialects/func/func_ops.mlir b/tests/filecheck/dialects/func/func_ops.mlir
@@ -71,4 +71,24 @@ builtin.module {
   // CHECK:       func.func public @arg_attrs(%{{.*}} : tensor<8x8xf64> {"llvm.noalias"}, %{{.*}} : tensor<8x8xf64> {"llvm.noalias"}, %{{.*}} : tensor<8x8xf64> {"llvm.noalias"}) -> tensor<8x8xf64> {
   // CHECK-NEXT:      return %{{.*}} : tensor<8x8xf64>
   // CHECK-NEXT:  }
+
+  func.func @output_attributes() -> (f32 {dialect.a = 0 : i32}, f32 {dialect.b = 0 : i32, dialect.c = 1 : i64}) {
+    %r1, %r2 = "test.op"() : () -> (f32, f32)
+    return %r1, %r2 : f32, f32
+  }
+
+  // CHECK:       func.func @output_attributes() -> (f32 {"dialect.a" = 0 : i32}, f32 {"dialect.b" = 0 : i32, "dialect.c" = 1 : i64}) {
+  // CHECK-NEXT:    %r1, %r2 = "test.op"() : () -> (f32, f32)
+  // CHECK-NEXT:    func.return %r1, %r2 : f32, f32
+  // CHECK-NEXT:  }
+
+  func.func @output_attribute_single() -> (f32 {dialect.a = 0 : i32}) {
+    %r1 = "test.op"() : () -> (f32)
+    return %r1: f32
+  }
+
+  // CHECK:       func.func @output_attribute_single() -> (f32 {"dialect.a" = 0 : i32}) {
+  // CHECK-NEXT:    %r1 = "test.op"() : () -> f32
+  // CHECK-NEXT:    func.return %r1 : f32
+  // CHECK-NEXT:  }
 }
diff --git a/tests/filecheck/dialects/func/func_ops_generic.mlir b/tests/filecheck/dialects/func/func_ops_generic.mlir
@@ -10,3 +10,13 @@
 // CHECK-NEXT: ^0(%arg0 : tensor<8x8xf64>, %arg1 : tensor<8x8xf64>):
 // CHECK-NEXT: "func.return"(%arg0, %arg1) : (tensor<8x8xf64>, tensor<8x8xf64>) -> ()
 // CHECK-NEXT: }) : () -> ()
+
+func.func @output_attributes() -> (f32 {dialect.a = 0 : i32}, f32 {dialect.b = 0 : i32, dialect.c = 1 : i64}) {
+    %r1, %r2 = "test.op"() : () -> (f32, f32)
+    return %r1, %r2 : f32, f32
+}
+
+// CHECK:       "func.func"() <{"sym_name" = "output_attributes", "function_type" = () -> (f32, f32), "res_attrs" = [{"dialect.a" = 0 : i32}, {"dialect.b" = 0 : i32, "dialect.c" = 1 : i64}]}> ({
+// CHECK-NEXT:      %r1, %r2 = "test.op"() : () -> (f32, f32)
+// CHECK-NEXT:      "func.return"(%r1, %r2) : (f32, f32) -> ()
+// CHECK-NEXT:  }) : () -> ()
diff --git a/tests/filecheck/mlir-conversion/with-mlir/dialects/func/func_ops.mlir b/tests/filecheck/mlir-conversion/with-mlir/dialects/func/func_ops.mlir
@@ -72,4 +72,14 @@ builtin.module {
   // CHECK:       func.func public @arg_attrs(%{{.*}}: tensor<8x8xf64> {"llvm.noalias"}, %{{.*}}: tensor<8x8xf64> {"llvm.noalias"}, %{{.*}}: tensor<8x8xf64> {"llvm.noalias"}) -> tensor<8x8xf64> {
   // CHECK-NEXT:      func.return %{{.*}} : tensor<8x8xf64>
   // CHECK-NEXT:  }
+
+  func.func @output_attributes() -> (f32 {dialect.a = 0 : i32}, f32 {dialect.b = 0 : i32, dialect.c = 1 : i64}) {
+    %r1, %r2 = "test.op"() : () -> (f32, f32)
+    return %r1, %r2 : f32, f32
+  }
+
+  // CHECK:       func.func @output_attributes() -> (f32 {"dialect.a" = 0 : i32}, f32 {"dialect.b" = 0 : i32, "dialect.c" = 1 : i64}) {
+  // CHECK-NEXT:    %0, %1 = "test.op"() : () -> (f32, f32)
+  // CHECK-NEXT:    func.return %0, %1 : f32, f32
+  // CHECK-NEXT:  }
 }