feature: riscv-v load and store

Signed-off-by: Ruige <[email protected]>
whutddk · Jul 26, 2023 · 7967e94 · 7967e94
1 parent ff7b534
commit 7967e94
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Showing 35 changed files with 3,585 additions and 3,297 deletions.
diff --git a/Makefile b/Makefile
@@ -244,6 +244,10 @@ fpuisa += rv64uf-v-move
 fpuisa += rv64uf-p-recoding
 fpuisa += rv64uf-v-recoding
 
+include ${R2}/tb/ci/vec/testList.mk
+
+
+
 isa ?= $(aluisa) $(bruisa) $(lsuisa) $(privisa) $(mulisa)# $(fpuisa) 
 # isa ?= $(fpuisa)
 
@@ -348,6 +352,11 @@ area: yosys
 	echo "{\n  \"schemaVersion\": 1, \n  \"label\": \"\", \n  \"message\": \""$(basename $(filter %.000000, $(shell cat $(R2)/generated/$(CONFIG)/stat.log) ))"\", \n  \"color\": \"a6bf94\" \n}" >> $(R2)/generated/$(CONFIG)/area.json
 # rm -f $(R2)/generated/$(CONFIG)/stat.log
 
+singleV: VSimTop
+	${R2}/generated/build/$(CONFIG)/VSimTop -w -l -p -f ./tb/ci/vec/$(TESTFILE)
+
+isaV:
+	$(foreach test, $(vecisa), ${R2}/generated/build/$(CONFIG)/VSimTop -l -f ./tb/ci/vec/$(test) || exit; )
 
 # lineCfg += Rift2300
 # lineCfg += Rift2310

diff --git a/src/main/scala/Config.scala b/src/main/scala/Config.scala
@@ -440,8 +440,45 @@ class Rift2360 extends Config((_, _, _) => {
 
 class Rift2370 extends Config((_, _, _) => {
   case RiftParamsKey => RiftSetting(
-    hasVector = false,
+    hasVector = true,
+
+    opChn = 2,
+    wbChn = 2,
+
+    pmpNum = 1,
+    hpmNum = 0,
+
+    icacheParameters = IcacheParameters(
+      bk = 1,
+      cb = 2,
+      cl = 8
+    ),
+
+    dcacheParameters = DcacheParameters(
+      bk = 2,
+      cb = 2,
+      cl = 8,
+      stEntry = 16,
+      sbEntry = 2,
+    ),
+
+    ifetchParameters = IFParameters(
+      uBTB_entry = 4,
+      btb_cl = 8,
+      bim_cl = 8,
+      ras_dp = 4,
+    ),
+
+    dptEntry = 4,
+
+    aluNum = 1,
+
+    xRegNum = 36,
+    fRegNum = 36,
+    tlbEntry = 4,
   )
+
+
 })
 
 class Rift2380 extends Config((_, _, _) => {

diff --git a/src/main/scala/Parameters.scala b/src/main/scala/Parameters.scala
@@ -91,18 +91,18 @@ abstract class DcacheBundle(implicit val p: Parameters) extends Bundle with HasD
 
 
 case class VectorParameters(
-  vlen: Int = 512,    //The number of bits in a single vector register
+  vlen: Int = 128,    //The number of bits in a single vector register
   elen: Int = 64,     //The maximum size in bits that can produce or consume 
   isEEW8: Boolean = true,
   isEEW16: Boolean = true,
   isEEW32: Boolean = true,
   isEEW64: Boolean = true,
   maxMUL : Int  = 8,
 
-  opChn: Int = 4,
-  wbChn: Int = 4,
+  // opChn: Int = 4,
+  // wbChn: Int = 4,
 
-  lsuEntry: Int = 16,
+  // lsuEntry: Int = 16,
 
 ){
 
@@ -127,7 +127,7 @@ case class VectorParameters(
   require( isPow2(maxMUL) )
   require(maxMUL >= 8)
 
-  val vlmax = (vlen / minEEW * maxMUL) -1
+  val vlmax = (vlen / minEEW * maxMUL)
   // val atw: Int = {
   //   if(isEEW8) {8}
   //   else if(isEEW16) {16}
@@ -242,6 +242,7 @@ case class RiftSetting(
   if(hasVector){
     // require( rnChn >= 2 )
     require( fpuNum > 0 )
+    require( dcacheParameters.stEntry >= vectorParameters.vlen/8, "Error! VStore will be stuck at Store Queue!" )
   }
 }
 

diff --git a/src/main/scala/rift2Chip/Rift2Chip.scala b/src/main/scala/rift2Chip/Rift2Chip.scala
@@ -72,7 +72,7 @@ class Rift2Chip(isFlatten: Boolean = false)(implicit p: Parameters) extends Lazy
   val nDevices = 31
   val i_plic = LazyModule( new Plic( nHarts = 1, nPriorities = 8, nDevices = nDevices ))
   val sifiveCache = LazyModule(new InclusiveCache(
-      cache = CacheParameters( level = 2, ways = 8, sets = 2048, blockBytes = l1DW/8, beatBytes = l1BeatBits/8, hintsSkipProbe = false ),
+      cache = CacheParameters( level = 2, ways = 2, sets = 64, blockBytes = l1DW/8, beatBytes = l1BeatBits/8, hintsSkipProbe = false ),
       micro = InclusiveCacheMicroParameters( writeBytes = memBeatBits/8, memCycles = 40, portFactor = 4),
       control = None
     ))