arch/risc-v: add uintreg_t

This introduces `uintreg_t` etc to have a type with same width as registers. Relevant sources are also updated to boot nuttx-ilp32. Signed-off-by: Yanfeng Liu <[email protected]>
yf13 · Jun 6, 2024 · 66853b8 · 66853b8
1 parent 8b8a09e
commit 66853b8
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Showing 11 changed files with 38 additions and 28 deletions.
diff --git a/arch/risc-v/include/irq.h b/arch/risc-v/include/irq.h
@@ -572,7 +572,7 @@ struct xcptcontext
    * another signal handler is executing will be ignored!
    */
 
-  uintptr_t *saved_regs;
+  uintreg_t *saved_regs;
 
 #ifndef CONFIG_BUILD_FLAT
   /* This is the saved address to use when returning from a user-space
@@ -611,21 +611,21 @@ struct xcptcontext
 
   /* Integer register save area */
 
-  uintptr_t *regs;
+  uintreg_t *regs;
 
   /* FPU register save area */
 
 #if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARCH_LAZYFPU)
-  uintptr_t fregs[FPU_XCPT_REGS];
+  uintreg_t fregs[FPU_XCPT_REGS];
 #endif
 
 #ifdef CONFIG_ARCH_RV_ISA_V
 #  if CONFIG_ARCH_RV_VECTOR_BYTE_LENGTH > 0
   /* There are 32 vector registers(v0 - v31) with vlenb length. */
 
-  uintptr_t vregs[VPU_XCPTC_SIZE];
+  uintreg_t vregs[VPU_XCPTC_SIZE];
 #  else
-  uintptr_t *vregs;
+  uintreg_t *vregs;
 #  endif
 #endif
 };
@@ -678,7 +678,7 @@ extern "C"
  * such value for each processor that can receive an interrupt.
  */
 
-EXTERN volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS];
+EXTERN volatile uintreg_t *g_current_regs[CONFIG_SMP_NCPUS];
 #define CURRENT_REGS (g_current_regs[up_cpu_index()])
 
 /****************************************************************************

diff --git a/arch/risc-v/include/types.h b/arch/risc-v/include/types.h
@@ -105,6 +105,11 @@ typedef unsigned long      _size_t;
 /* This is the size of the interrupt state save returned by irqsave().  */
 
 typedef unsigned long long  irqstate_t;
+
+/* Integer with same width as CPU registers. */
+
+typedef _int64_t            intreg_t;
+typedef _uint64_t           uintreg_t;
 #else
 /* A size is 4 bytes */
 
@@ -129,6 +134,11 @@ typedef unsigned int       _size_t;
 /* This is the size of the interrupt state save returned by irqsave().  */
 
 typedef unsigned int       irqstate_t;
+
+/* Integer with save width as CPU registers. */
+
+typedef _int32_t           intreg_t;
+typedef _uint32_t          uintreg_t;
 #endif
 
 #endif /* __ASSEMBLY__ */

diff --git a/arch/risc-v/src/common/riscv_doirq.c b/arch/risc-v/src/common/riscv_doirq.c
@@ -56,7 +56,7 @@
  * Public Functions
  ****************************************************************************/
 
-uintptr_t *riscv_doirq(int irq, uintptr_t *regs)
+uintreg_t *riscv_doirq(int irq, uintreg_t *regs)
 {
   board_autoled_on(LED_INIRQ);
 #ifdef CONFIG_SUPPRESS_INTERRUPTS
@@ -119,7 +119,7 @@ uintptr_t *riscv_doirq(int irq, uintptr_t *regs)
        * that a context switch occurred during interrupt processing.
        */
 
-      regs = (uintptr_t *)CURRENT_REGS;
+      regs = (uintreg_t *)CURRENT_REGS;
     }
 
   /* Set CURRENT_REGS to NULL to indicate that we are no longer in an

diff --git a/arch/risc-v/src/common/riscv_fork.c b/arch/risc-v/src/common/riscv_fork.c
@@ -110,7 +110,7 @@ pid_t riscv_fork(const struct fork_s *context)
   uintptr_t stacktop;
   uintptr_t stackutil;
 #ifdef CONFIG_ARCH_FPU
-  uintptr_t *fregs;
+  uintreg_t *fregs;
 #endif
 
   sinfo("s0:%" PRIxREG " s1:%" PRIxREG " s2:%" PRIxREG " s3:%" PRIxREG ""

diff --git a/arch/risc-v/src/common/riscv_initialize.c b/arch/risc-v/src/common/riscv_initialize.c
@@ -32,7 +32,7 @@
  * Public Data
  ****************************************************************************/
 
-volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS];
+volatile uintreg_t *g_current_regs[CONFIG_SMP_NCPUS];
 
 /****************************************************************************
  * Private Functions

diff --git a/arch/risc-v/src/common/riscv_initialstate.c b/arch/risc-v/src/common/riscv_initialstate.c
@@ -131,7 +131,7 @@ void up_initial_state(struct tcb_s *tcb)
     }
 #endif
 
-  xcp->regs = (uintptr_t *)(topstack - XCPTCONTEXT_SIZE);
+  xcp->regs = (uintreg_t *)(topstack - XCPTCONTEXT_SIZE);
   memset(xcp->regs, 0, XCPTCONTEXT_SIZE);
 
   /* Save the initial stack pointer.  Hmmm.. the stack is set to the very

diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h
@@ -96,7 +96,7 @@
  * only a reference stored in TCB.
  */
 
-#define riscv_savestate(regs) (regs = (uintptr_t *)CURRENT_REGS)
+#define riscv_savestate(regs) (regs = (uintreg_t *)CURRENT_REGS)
 #define riscv_restorestate(regs) (CURRENT_REGS = regs)
 
 /* Determine which (if any) console driver to use.  If a console is enabled
@@ -244,12 +244,12 @@ void riscv_exception_attach(void);
 
 #ifdef CONFIG_ARCH_FPU
 void riscv_fpuconfig(void);
-void riscv_savefpu(uintptr_t *regs, uintptr_t *fregs);
-void riscv_restorefpu(uintptr_t *regs, uintptr_t *fregs);
+void riscv_savefpu(uintreg_t *regs, uintreg_t *fregs);
+void riscv_restorefpu(uintreg_t *regs, uintreg_t *fregs);
 
 /* Get FPU register save area */
 
-static inline uintptr_t *riscv_fpuregs(struct tcb_s *tcb)
+static inline uintreg_t *riscv_fpuregs(struct tcb_s *tcb)
 {
 #ifdef CONFIG_ARCH_LAZYFPU
   /* With lazy FPU the registers are simply in tcb */
@@ -258,7 +258,7 @@ static inline uintptr_t *riscv_fpuregs(struct tcb_s *tcb)
 #else
   /* Otherwise they are after the integer registers */
 
-  return (uintptr_t *)((uintptr_t)tcb->xcp.regs + INT_XCPT_SIZE);
+  return (uintreg_t *)((uintptr_t)tcb->xcp.regs + INT_XCPT_SIZE);
 #endif
 }
 #else
@@ -290,7 +290,7 @@ static inline uintptr_t *riscv_vpuregs(struct tcb_s *tcb)
 
 static inline void riscv_savecontext(struct tcb_s *tcb)
 {
-  tcb->xcp.regs = (uintptr_t *)CURRENT_REGS;
+  tcb->xcp.regs = (uintreg_t *)CURRENT_REGS;
 
 #ifdef CONFIG_ARCH_FPU
   /* Save current process FPU state to TCB */
@@ -307,7 +307,7 @@ static inline void riscv_savecontext(struct tcb_s *tcb)
 
 static inline void riscv_restorecontext(struct tcb_s *tcb)
 {
-  CURRENT_REGS = (uintptr_t *)tcb->xcp.regs;
+  CURRENT_REGS = (uintreg_t *)tcb->xcp.regs;
 
 #ifdef CONFIG_ARCH_FPU
   /* Restore FPU state for next process */
@@ -384,7 +384,7 @@ void riscv_netinitialize(void);
 
 /* Exception Handler ********************************************************/
 
-uintptr_t *riscv_doirq(int irq, uintptr_t *regs);
+uintreg_t *riscv_doirq(int irq, uintreg_t *regs);
 int riscv_exception(int mcause, void *regs, void *args);
 int riscv_fillpage(int mcause, void *regs, void *args);
 int riscv_misaligned(int irq, void *context, void *arg);

diff --git a/arch/risc-v/src/common/riscv_schedulesigaction.c b/arch/risc-v/src/common/riscv_schedulesigaction.c
@@ -136,10 +136,10 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
                * been delivered.
                */
 
-              CURRENT_REGS = (uintptr_t *)((uintptr_t)CURRENT_REGS -
+              CURRENT_REGS = (uintreg_t *)((uintptr_t)CURRENT_REGS -
                                                       XCPTCONTEXT_SIZE);
 
-              memcpy((uintptr_t *)CURRENT_REGS, tcb->xcp.saved_regs,
+              memcpy((uintreg_t *)CURRENT_REGS, tcb->xcp.saved_regs,
                      XCPTCONTEXT_SIZE);
 
               /* Then set up to vector to the trampoline with interrupts
@@ -190,7 +190,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
            * delivered.
            */
 
-          tcb->xcp.regs = (uintptr_t *)((uintptr_t)tcb->xcp.regs -
+          tcb->xcp.regs = (uintreg_t *)((uintptr_t)tcb->xcp.regs -
                                                    XCPTCONTEXT_SIZE);
 
           memcpy(tcb->xcp.regs, tcb->xcp.saved_regs, XCPTCONTEXT_SIZE);

diff --git a/arch/risc-v/src/common/riscv_sigdeliver.c b/arch/risc-v/src/common/riscv_sigdeliver.c
@@ -55,7 +55,7 @@
 void riscv_sigdeliver(void)
 {
   struct tcb_s *rtcb = this_task();
-  uintptr_t *regs = rtcb->xcp.saved_regs;
+  uintreg_t *regs = rtcb->xcp.saved_regs;
 
 #ifdef CONFIG_SMP
   /* In the SMP case, we must terminate the critical section while the signal

diff --git a/arch/risc-v/src/common/riscv_swint.c b/arch/risc-v/src/common/riscv_swint.c
@@ -114,7 +114,7 @@ static void dispatch_syscall(void)
 
 int riscv_swint(int irq, void *context, void *arg)
 {
-  uintptr_t *regs = (uintptr_t *)context;
+  uintreg_t *regs = (uintreg_t *)context;
 
   DEBUGASSERT(regs && regs == CURRENT_REGS);
 
@@ -150,7 +150,7 @@ int riscv_swint(int irq, void *context, void *arg)
 
       case SYS_restore_context:
         {
-          struct tcb_s *next = (struct tcb_s *)regs[REG_A1];
+          struct tcb_s *next = (struct tcb_s *)(uintptr_t)regs[REG_A1];
 
           DEBUGASSERT(regs[REG_A1] != 0);
           riscv_restorecontext(next);
@@ -176,8 +176,8 @@ int riscv_swint(int irq, void *context, void *arg)
 
       case SYS_switch_context:
         {
-          struct tcb_s *prev = (struct tcb_s *)regs[REG_A1];
-          struct tcb_s *next = (struct tcb_s *)regs[REG_A2];
+          struct tcb_s *prev = (struct tcb_s *)(uintptr_t)regs[REG_A1];
+          struct tcb_s *next = (struct tcb_s *)(uintptr_t)regs[REG_A2];
 
           DEBUGASSERT(regs[REG_A1] != 0 && regs[REG_A2] != 0);
           riscv_savecontext(prev);

diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c b/arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c
@@ -53,7 +53,7 @@
  * riscv_dispatch_irq
  ****************************************************************************/
 
-void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
+void *riscv_dispatch_irq(uintreg_t vector, uintreg_t *regs)
 {
   int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);