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Popular repositories Loading

  1. basics-graphics-music basics-graphics-music Public

    FPGA exercise for beginners

    SystemVerilog 143 121

  2. systemverilog-homework systemverilog-homework Public

    SystemVerilog language-oriented exercises

    SystemVerilog 132 139

  3. yrv-plus yrv-plus Public

    Forked from montedalrymple/yrv

    Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.

    Verilog 26 14

  4. 2019-examples 2019-examples Public

    Verilog 10 4

  5. schoolRISCV schoolRISCV Public

    Forked from zhelnio/schoolRISCV

    CPU microarchitecture, step by step

    Makefile 5

  6. 2017-tomsk-novosibirsk-astana 2017-tomsk-novosibirsk-astana Public

    Verilog examples and other materials for seminars in Tomsk, Novosibirsk and Astana

    Verilog 4 1