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yuri-panchulyuri-panchul
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Merge pull request #237 from felloryz/main
Fix Quartus synth error after previous PR
2 parents 904045c + a3b579a commit e564ed9

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‎peripherals/dvi.sv‎

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`include "dvi_config.svh"
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module dvi_top (
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input logic serial_clk_i,
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input logic pixel_clk_i,
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input logic rst_i,
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input logic [COLOR_W-1:0] red_i,
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input logic [COLOR_W-1:0] green_i,
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input logic [COLOR_W-1:0] blue_i,
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output logic [X_POS_W-1:0] x_o,
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output logic [Y_POS_W-1:0] y_o,
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output logic red_serial_o,
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output logic green_serial_o,
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output logic blue_serial_o
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);
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logic hsync;
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logic vsync;
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logic visible_range;
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logic hsync_r;
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logic vsync_r;
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logic visible_range_r;
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logic [ 9:0] red_tmds;
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logic [ 9:0] green_tmds;
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logic [ 9:0] blue_tmds;
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// ------------------------------------------------------------------------
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// Sync
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// ------------------------------------------------------------------------
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dvi_sync i_dvi_sync (
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.clk_i ( pixel_clk_i ),
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.rst_i ( rst_i ),
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.hsync_o ( hsync ),
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.vsync_o ( vsync ),
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.pixel_x_o ( x_o ),
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.pixel_y_o ( y_o ),
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.visible_range_o ( visible_range )
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);
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// ------------------------------------------------------------------------
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// Encode
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// ------------------------------------------------------------------------
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// Delay hsync/vsync and visible_range by 1 clock cycle to account for color
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// delay in image_gen
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always_ff @(posedge pixel_clk_i) begin
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if (rst_i) begin
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hsync_r <= '0;
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vsync_r <= '0;
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visible_range_r <= '0;
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end else begin
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hsync_r <= hsync;
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vsync_r <= vsync;
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visible_range_r <= visible_range;
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end
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end
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tmds_encoder blue_encoder (
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.clk_i ( pixel_clk_i ),
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.rst_i ( rst_i ),
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.C0 ( hsync_r ),
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.C1 ( vsync_r ),
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.DE ( visible_range_r ),
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.D ( blue_i ),
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.q_out ( blue_tmds )
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);
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tmds_encoder green_encoder (
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.clk_i ( pixel_clk_i ),
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.rst_i ( rst_i ),
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.C0 ( 1'b0 ),
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.C1 ( 1'b0 ),
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.DE ( visible_range_r ),
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.D ( green_i ),
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.q_out ( green_tmds )
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);
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tmds_encoder red_encoder (
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.clk_i ( pixel_clk_i ),
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.rst_i ( rst_i ),
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.C0 ( 1'b0 ),
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.C1 ( 1'b0 ),
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.DE ( visible_range_r ),
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.D ( red_i ),
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.q_out ( red_tmds )
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);
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// ------------------------------------------------------------------------
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// Serialize
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// ------------------------------------------------------------------------
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serializer #(
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.DATA_W ( 10 )
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) blue_serializer (
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.clk_i ( serial_clk_i ),
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.rst_i ( rst_i ),
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.data_i ( blue_tmds ),
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.data_o ( blue_serial_o )
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);
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serializer #(
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.DATA_W ( 10 )
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) green_serializer (
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.clk_i ( serial_clk_i ),
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.rst_i ( rst_i ),
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.data_i ( green_tmds ),
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.data_o ( green_serial_o )
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);
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serializer #(
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.DATA_W ( 10 )
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) red_serializer (
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.clk_i ( serial_clk_i ),
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.rst_i ( rst_i ),
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.data_i ( red_tmds ),
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.data_o ( red_serial_o )
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);
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endmodule
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module dvi_sync (
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input logic clk_i,
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input logic rst_i,
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output logic hsync_o,
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output logic vsync_o,
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output logic [X_POS_W-1:0] pixel_x_o,
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output logic [Y_POS_W-1:0] pixel_y_o,
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output logic visible_range_o
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);
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logic h_cnt_max;
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logic [HS_W-1:0] h_cnt_next;
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logic [HS_W-1:0] h_cnt;
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logic [VS_W-1:0] v_cnt_next;
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logic [VS_W-1:0] v_cnt;
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always_comb begin
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h_cnt_max = h_cnt == (H_TOTAL - 1);
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h_cnt_next = h_cnt_max ? '0 : h_cnt + 1'b1;
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v_cnt_next = v_cnt;
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if (h_cnt_max) begin
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v_cnt_next = v_cnt + 1'b1;
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if (v_cnt == (V_TOTAL - 1))
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v_cnt_next = '0;
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end
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end
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always_ff @(posedge clk_i) begin
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if (rst_i) begin
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h_cnt <= '0;
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v_cnt <= '0;
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end else begin
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h_cnt <= h_cnt_next;
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v_cnt <= v_cnt_next;
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end
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end
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// Register outputs
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always_ff @(posedge clk_i)
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if (rst_i) begin
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hsync_o <= '0;
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vsync_o <= '0;
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pixel_x_o <= '0;
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pixel_y_o <= '0;
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visible_range_o <= '0;
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end else begin
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hsync_o <= !(h_cnt_next >= HSYNC_START && h_cnt_next < HSYNC_END);
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vsync_o <= !(v_cnt_next >= VSYNC_START && v_cnt_next < VSYNC_END);
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pixel_x_o <= (h_cnt_next > SCREEN_H_RES - 1) ? '0 : X_POS_W'(h_cnt_next);
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pixel_y_o <= (v_cnt_next > SCREEN_V_RES - 1) ? '0 : Y_POS_W'(v_cnt_next);
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visible_range_o <= ((h_cnt_next < SCREEN_H_RES) && (v_cnt_next < SCREEN_V_RES));
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end
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endmodule
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module serializer #(
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parameter DATA_W = 10
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) (
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input logic clk_i,
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input logic rst_i,
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input logic [DATA_W-1:0] data_i,
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output logic data_o
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);
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localparam CNT_MAX = DATA_W - 1;
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logic [DATA_W-1:0] shift_reg;
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logic [ 3:0] cnt;
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logic load;
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assign load = cnt == CNT_MAX;
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always_ff @(posedge clk_i) begin
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if (rst_i) begin
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cnt <= '0;
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end else if (load) begin
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cnt <= '0;
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end else begin
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cnt <= cnt + 1'b1;
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end
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end
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always_ff @(posedge clk_i) begin
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if (rst_i) begin
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shift_reg <= '0;
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end else if (load) begin
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shift_reg <= data_i;
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end else begin
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shift_reg <= { 1'b0, shift_reg[DATA_W-1:1] };
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end
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end
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assign data_o = shift_reg[0];
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endmodule
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module tmds_encoder (
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input logic clk_i,
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input logic rst_i,
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input logic C0,
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input logic C1,
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input logic DE,
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input logic [7:0] D,
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output logic [9:0] q_out
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);
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localparam W_CNT = 8;
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logic signed [W_CNT-1:0] cnt;
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logic signed [W_CNT-1:0] cnt_next;
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logic [8:0] q_m;
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logic [9:0] q_next;
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logic [3:0] N1D;
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logic [3:0] N1_qm;
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logic [3:0] N0_qm;
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always_comb begin
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N1D = 4'(D[0]) + 4'(D[1]) + 4'(D[2]) + 4'(D[3])
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+ 4'(D[4]) + 4'(D[5]) + 4'(D[6]) + 4'(D[7]);
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q_m[0] = D[0];
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if ((N1D > 4) || (N1D == 4 && ~D[0])) begin
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// verilator lint_off ALWCOMBORDER
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q_m[8] = 1'b0;
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for (int i = 0; i < 7; i++) begin
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q_m[i + 1] = q_m[i] ~^ D[i + 1];
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end
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// verilator lint_on ALWCOMBORDER
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end else begin
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q_m[8] = 1'b1;
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for (int i = 0; i < 7; i++) begin
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q_m[i + 1] = q_m[i] ^ D[i + 1];
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end
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end
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N1_qm = 4'(q_m[0]) + 4'(q_m[1]) + 4'(q_m[2]) + 4'(q_m[3])
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+ 4'(q_m[4]) + 4'(q_m[5]) + 4'(q_m[6]) + 4'(q_m[7]);
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N0_qm = 4'(!q_m[0]) + 4'(!q_m[1]) + 4'(!q_m[2]) + 4'(!q_m[3])
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+ 4'(!q_m[4]) + 4'(!q_m[5]) + 4'(!q_m[6]) + 4'(!q_m[7]);
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if (DE) begin
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if ((cnt == 0) || (N1_qm == N0_qm)) begin
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q_next[9] = ~q_m[8];
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q_next[8] = q_m[8];
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q_next[7:0] = q_m[8] ? q_m[7:0] : ~q_m[7:0];
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if (~q_m[8]) begin
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cnt_next = cnt + W_CNT'(N0_qm) - W_CNT'(N1_qm);
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end else begin
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cnt_next = cnt + W_CNT'(N1_qm) - W_CNT'(N0_qm);
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end
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end else begin
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if (((cnt > 0) && (N1_qm > N0_qm)) ||
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((cnt < 0) && (N0_qm > N1_qm))) begin
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q_next[9] = 1'b1;
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q_next[8] = q_m[8];
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q_next[7:0] = ~q_m[7:0];
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cnt_next = cnt + (W_CNT'(q_m[8]) << 1) +
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W_CNT'(N0_qm) - W_CNT'(N1_qm);
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end else begin
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q_next[9] = 1'b0;
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q_next[8] = q_m[8];
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q_next[7:0] = q_m[7:0];
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cnt_next = cnt - (W_CNT'({~q_m[8]}) << 1) +
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W_CNT'(N1_qm) - W_CNT'(N0_qm);
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end
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end
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end else begin
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cnt_next = '0;
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case ({C1, C0})
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2'b00: q_next = 10'b1101010100;
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2'b01: q_next = 10'b0010101011;
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2'b10: q_next = 10'b0101010100;
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2'b11: q_next = 10'b1010101011;
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endcase
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end
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end
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always_ff @(posedge clk_i) begin
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if (rst_i) begin
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cnt <= '0;
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end else begin
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cnt <= cnt_next;
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end
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end
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always_ff @(posedge clk_i) begin
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q_out <= q_next;
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end
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endmodule

‎peripherals/dvi_config.svh‎

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`ifndef DVI_CONFIG_SVH
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`define DVI_CONFIG_SVH
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parameter SCREEN_H_RES = 640;
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parameter SCREEN_V_RES = 480;
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parameter HSYNC_PULSE = 96;
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parameter H_FRONT_PORCH = 16;
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parameter H_BACK_PORCH = 48;
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parameter H_BORDER = 0;
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parameter VSYNC_PULSE = 2;
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parameter V_FRONT_PORCH = 10;
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parameter V_BACK_PORCH = 33;
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parameter V_BORDER = 0;
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// HSYNC
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parameter HSYNC_START = SCREEN_H_RES + H_BORDER + H_FRONT_PORCH;
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parameter HSYNC_END = HSYNC_START + HSYNC_PULSE;
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parameter H_TOTAL = HSYNC_END + H_BACK_PORCH + H_BORDER;
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// VSYNC
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parameter VSYNC_START = SCREEN_V_RES + V_BORDER + V_FRONT_PORCH;
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parameter VSYNC_END = VSYNC_START + VSYNC_PULSE;
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parameter V_TOTAL = VSYNC_END + V_BACK_PORCH + V_BORDER;
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parameter X_POS_W = $clog2(SCREEN_H_RES + 1);
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parameter Y_POS_W = $clog2(SCREEN_V_RES + 1);
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parameter HS_W = $clog2(H_TOTAL + 1);
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parameter VS_W = $clog2(V_TOTAL + 1);
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parameter COLOR_W = 8;
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`endif

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