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Update cmsis 5.9.0 #18

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Update cmsis 5.9.0 #18

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10946e7
Update DSP
geekbozu Jul 4, 2022
bba1d33
Updated NN
geekbozu Jul 4, 2022
0d87801
Update Cores
geekbozu Jul 4, 2022
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8 changes: 4 additions & 4 deletions CMSIS/Core/Include/cmsis_version.h
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.4
* @date 23. July 2019
* @version V5.0.5
* @date 02. February 2022
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
* Copyright (c) 2009-2022 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
Expand Down Expand Up @@ -33,7 +33,7 @@

/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif
29 changes: 20 additions & 9 deletions CMSIS/Core/Include/core_armv81mml.h
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_armv81mml.h
* @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File
* @version V1.4.1
* @date 04. June 2021
* @version V1.4.2
* @date 13. October 2021
******************************************************************************/
/*
* Copyright (c) 2018-2021 Arm Limited. All rights reserved.
Expand Down Expand Up @@ -526,7 +526,7 @@ typedef struct
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
Expand All @@ -535,7 +535,10 @@ typedef struct
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
uint32_t RESERVED3[92U];
uint32_t RESERVED7[21U];
__IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
__IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
uint32_t RESERVED3[69U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
__IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */
uint32_t RESERVED4[14U];
Expand Down Expand Up @@ -1490,15 +1493,14 @@ typedef struct
uint32_t RESERVED11[108];
__IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */
__IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */
uint32_t RESERVED12[4];
uint32_t RESERVED12[3];
__IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */
__IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */
uint32_t RESERVED13[3];
__IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */
__IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */
__IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */
__IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */
uint32_t RESERVED14[3];
__IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */
__IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */
__IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */
__IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */
__IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */
__IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */
Expand Down Expand Up @@ -3158,6 +3160,15 @@ typedef struct
/*@} */


/**
\ingroup CMSIS_core_register
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
\brief Register alias definitions for backwards compatibility.
@{
*/
#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
/*@} */


/*******************************************************************************
* Hardware Abstraction Layer
Expand Down
20 changes: 16 additions & 4 deletions CMSIS/Core/Include/core_armv8mml.h
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_armv8mml.h
* @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
* @version V5.2.2
* @date 04. June 2021
* @version V5.2.3
* @date 13. October 2021
******************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
Expand Down Expand Up @@ -519,7 +519,7 @@ typedef struct
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
Expand All @@ -528,7 +528,10 @@ typedef struct
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
uint32_t RESERVED3[92U];
uint32_t RESERVED7[21U];
__IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
__IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
uint32_t RESERVED3[69U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
uint32_t RESERVED4[15U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
Expand Down Expand Up @@ -2182,6 +2185,15 @@ typedef struct
/*@} */


/**
\ingroup CMSIS_core_register
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
\brief Register alias definitions for backwards compatibility.
@{
*/
#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
/*@} */


/*******************************************************************************
* Hardware Abstraction Layer
Expand Down
20 changes: 16 additions & 4 deletions CMSIS/Core/Include/core_cm33.h
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_cm33.h
* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
* @version V5.2.2
* @date 04. June 2021
* @version V5.2.3
* @date 13. October 2021
******************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
Expand Down Expand Up @@ -519,7 +519,7 @@ typedef struct
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
Expand All @@ -528,7 +528,10 @@ typedef struct
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
uint32_t RESERVED3[92U];
uint32_t RESERVED7[21U];
__IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
__IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
uint32_t RESERVED3[69U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
uint32_t RESERVED4[15U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
Expand Down Expand Up @@ -2257,6 +2260,15 @@ typedef struct
/*@} */


/**
\ingroup CMSIS_core_register
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
\brief Register alias definitions for backwards compatibility.
@{
*/
#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
/*@} */


/*******************************************************************************
* Hardware Abstraction Layer
Expand Down
20 changes: 16 additions & 4 deletions CMSIS/Core/Include/core_cm35p.h
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file core_cm35p.h
* @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File
* @version V1.1.2
* @date 04. June 2021
* @version V1.1.3
* @date 13. October 2021
******************************************************************************/
/*
* Copyright (c) 2018-2021 Arm Limited. All rights reserved.
Expand Down Expand Up @@ -519,7 +519,7 @@ typedef struct
__IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
Expand All @@ -528,7 +528,10 @@ typedef struct
__IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
__IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
uint32_t RESERVED3[92U];
uint32_t RESERVED7[21U];
__IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
__IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
uint32_t RESERVED3[69U];
__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
uint32_t RESERVED4[15U];
__IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
Expand Down Expand Up @@ -2257,6 +2260,15 @@ typedef struct
/*@} */


/**
\ingroup CMSIS_core_register
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
\brief Register alias definitions for backwards compatibility.
@{
*/
#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */
/*@} */


/*******************************************************************************
* Hardware Abstraction Layer
Expand Down
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