extend cache interface to support xtensa coherency architecture #68140

nashif · 2024-01-25T23:47:53Z

This move custom cache calls implemented via soc APIs to a generic interface that can be used to abstract the cache calls.
Eliminate more use of z_soc_* call

cache: introduce coherent cache interface
xtensa: move to use system cache API support for coherency

carlocaione

nits

carlocaione · 2024-01-26T08:45:40Z

arch/Kconfig

+	depends on CPU_HAS_CACHE_COHERENCY
+	default y
+	help
+	  Cache coherency


maybe a more verbose help?

carlocaione · 2024-01-26T08:47:00Z

include/zephyr/arch/cache.h

+bool arch_cache_is_ptr_cached(void *ptr);
+
+#define cache_is_ptr_cached(ptr) arch_cache_is_ptr_cached(ptr)
+
+
+bool arch_cache_is_ptr_uncached(void *ptr);
+
+#define cache_is_ptr_uncached(ptr) arch_cache_is_ptr_uncached(ptr)


remove the space between bool and define (like it is done in the following lines).

zephyrbot · 2024-01-26T13:22:16Z

The following west manifest projects have been modified in this Pull Request:

Name	Old Revision	New Revision	Diff
sof	zephyrproject-rtos/sof@`7a0ff76` (zephyr_wip)	zephyrproject-rtos/sof@`0606152` (zephyr)	zephyrproject-rtos/[email protected]

Note: This message is automatically posted and updated by the Manifest GitHub Action.

lgirdwood

LGTM.

marc-hb

HW test results don't look good in thesofproject/sof#8824 but as stated before, they don't look good already in the first place so it's practically impossible to tell whether this PR makes them better or worse or no difference.

include/zephyr/arch/cache.h

nashif · 2024-02-01T12:55:11Z

so it's practically impossible to tell whether this PR makes them better or worse or no difference.

This PR is not supposed to fix or deal with existing issues in SOF. This just adds a level of abstraction and removes z_soc_ and arch_xtensa_ usages in SOF which has the goal of running on architectures other than xtensa.

marc-hb

so it's practically impossible to tell whether this PR makes them [the tests] ~~better or~~ worse or no difference.

This PR is not supposed to fix or deal with existing issues in SOF.

I meant "worse or no difference", sorry.

This just adds a level of abstraction and removes z_soc_ and arch_xtensa_ usages in SOF which ...

I understand. Testing the SOF main branch is unfortunately not in a position to prove that and the lack of any regression yet. SOF validation status: unknown.

On the other hand, I triple checked the adress warnings from sparse in cache.h and they do come from this PR.

include/zephyr/arch/cache.h

nashif · 2024-02-02T01:15:30Z

On the other hand, I triple checked the adress warnings from sparse in cache.h and they do come from this PR.

yes, fedora seems to have an old version of sparse, installed from git now and I am getting the same thing.

marc-hb · 2024-02-02T01:25:48Z

yes, fedora seems to have an old version of sparse, installed from git now and I am getting the same thing.

Mystery solved!

We use https://github.com/thesofproject/sparse which I updated recently and is not far from https://git.kernel.org/pub/scm/devel/sparse/sparse.git/log/. There's an extremely recent fix for an infinite loop.

I can update https://github.com/thesofproject/sparse if needed.

sparse regressions are fixed in 9e1fbcdee941

lyakh · 2024-02-02T06:54:25Z

include/zephyr/cache.h

+{
+#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_CACHE_DOUBLEMAP)
+	return cache_is_ptr_cached(ptr);
+#endif


should this be an #else? With the #if above being true we're getting unreachable code. Same everywhere below. One could also use if (IS_ENABLED(CONFIG_...)) instead

lyakh · 2024-02-02T06:59:38Z

drivers/ipm/ipm_cavs_host.c

-		+ CONFIG_IPM_CAVS_HOST_OUTBOX_OFFSET));
+	uint32_t *buf = (uint32_t *)sys_cache_uncached_ptr_get(
+			(void *)((uint32_t)mw0_config->mem_base
+			+ CONFIG_IPM_CAVS_HOST_OUTBOX_OFFSET));


doesn't sparse warn about this? Is this file compiled? The argument of sys_cache_uncached_ptr_get() should be a cached pointer, so the type-case should be (void __sparse_cache *) there (in line 54 in this case instead of (void *)

lyakh · 2024-02-02T06:59:58Z

drivers/ipm/ipm_cavs_host.c

@@ -108,7 +110,7 @@ static bool ipc_handler(const struct device *dev, void *arg,
 		return -ENODEV;
 	}
 	const struct mem_win_config *mw1_config = mw1->config;
-	uint32_t *msg = arch_xtensa_uncached_ptr((void *)mw1_config->mem_base);
+	uint32_t *msg = sys_cache_uncached_ptr_get((void *)mw1_config->mem_base);


lyakh · 2024-02-02T07:04:40Z

tests/boards/intel_adsp/smoke/src/cpus.c

 		      "stack memory not cached");
-	zassert_not_equal(&tag, arch_xtensa_uncached_ptr((void *)&tag),
+	zassert_not_equal(&tag, sys_cache_uncached_ptr_get((void *)&tag),


argument should be __sparse_cache

lyakh · 2024-02-02T07:04:59Z

tests/boards/intel_adsp/smoke/src/cpus.c

 		      "stack memory not cached");
-	zassert_equal(&static_tag, arch_xtensa_uncached_ptr((void *)&static_tag),
+	zassert_equal(&static_tag, sys_cache_uncached_ptr_get((void *)&static_tag),


lyakh · 2024-02-02T07:06:00Z

tests/boards/intel_adsp/smoke/src/cpus.c

-	volatile int *ctag = (volatile int *)arch_xtensa_cached_ptr((void *)&tag);
-	volatile int *utag = (volatile int *)arch_xtensa_uncached_ptr((void *)&tag);
+	volatile int *ctag = (volatile int *)sys_cache_cached_ptr_get((void *)&tag);
+	volatile int *utag = (volatile int *)sys_cache_uncached_ptr_get((void *)&tag);


all "uncached get" have a cached pointer as their argument, so the latter one should have (void __sparce_cache *) in the argument conversion

Introduce a set of cache APIs used on architectures with cache incoherency. Signed-off-by: Anas Nashif <[email protected]>

Remove custom implementation and use system cache interface instead. Signed-off-by: Anas Nashif <[email protected]>

point to d40682678b7378fb930ca5535ccd2ce667ed5c27. Signed-off-by: Anas Nashif <[email protected]>

nashif requested review from dcpleung and andyross as code owners January 25, 2024 23:47

zephyrbot added platform: Intel ADSP Intel Audio platforms area: Cache area: IPM Inter-Processor Mailbox area: Architectures area: Console area: Xtensa Xtensa Architecture area: Memory Management labels Jan 25, 2024

zephyrbot requested review from carlocaione, ceolin, edersondisouza, jxstelter, kv2019i, lgirdwood, lyakh, marc-hb, marcinszkudlinski, softwarecki and tmleman January 25, 2024 23:48

zephyrbot assigned dcpleung Jan 25, 2024

nashif mentioned this pull request Jan 25, 2024

zephyr: use arch_xtensa_uncached_ptr/arch_xtensa_cached_ptr thesofproject/sof#8769

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carlocaione requested changes Jan 26, 2024

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nashif force-pushed the topic/cache/coherency1 branch 2 times, most recently from fd6269e to 354ccdd Compare January 26, 2024 13:21

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lgirdwood previously approved these changes Jan 26, 2024

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nashif dismissed lgirdwood’s stale review via 8fd6d0b January 26, 2024 16:34

nashif dismissed andyross’s stale review via 3284d86 January 31, 2024 22:13

nashif force-pushed the topic/cache/coherency1 branch from c2268a9 to 3284d86 Compare January 31, 2024 22:13

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nashif dismissed stale reviews from carlocaione, cfriedt, and dcpleung via 06b14ab February 2, 2024 01:19

nashif force-pushed the topic/cache/coherency1 branch from 3284d86 to 06b14ab Compare February 2, 2024 01:19

nashif force-pushed the topic/cache/coherency1 branch 2 times, most recently from 597e6d3 to 9e1fbcd Compare February 2, 2024 02:12

nashif requested review from marc-hb and dcpleung February 2, 2024 02:53

lyakh reviewed Feb 2, 2024

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nashif added 3 commits February 2, 2024 06:27

cache: introduce incoherent cache interface

9865dfe

Introduce a set of cache APIs used on architectures with cache incoherency. Signed-off-by: Anas Nashif <[email protected]>

xtensa: move to use system cache API support for coherency

3867abc

Remove custom implementation and use system cache interface instead. Signed-off-by: Anas Nashif <[email protected]>

manifest: update sof sha in manifest

759ff94

point to d40682678b7378fb930ca5535ccd2ce667ed5c27. Signed-off-by: Anas Nashif <[email protected]>

nashif force-pushed the topic/cache/coherency1 branch from 9e1fbcd to 759ff94 Compare February 2, 2024 11:27

zephyrbot added the area: Documentation Infrastructure label Feb 2, 2024

nashif added this to the v3.6.0 milestone Feb 2, 2024

dcpleung approved these changes Feb 2, 2024

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cfriedt approved these changes Feb 3, 2024

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nashif merged commit f6adaf5 into zephyrproject-rtos:main Feb 3, 2024
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extend cache interface to support xtensa coherency architecture #68140

extend cache interface to support xtensa coherency architecture #68140

nashif commented Jan 25, 2024

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extend cache interface to support xtensa coherency architecture #68140

extend cache interface to support xtensa coherency architecture #68140

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