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1.13.1
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@amykyta3 amykyta3 released this 27 Sep 04:45
v1.13.1
203ea87

Bug Fixes

  • Fix Verilog Preprocessor regression when checking for trailing text after include directives in files that use Windows CRLF newlines (#65)
  • Fix Verilog Preprocessor bug when processing macro text in files that use Windows CRLF newlines (#65)
  • Fix missed check on Verilog Preprocessor's conditional state when processing macro expansion and undef directives. (#64)
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