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make sampleUnfiltered respect ExpectOptions and fix eqWishboneS2M bug #157

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Merged
lmbollen merged 2 commits into from
Jul 17, 2025
Merged

make sampleUnfiltered respect ExpectOptions and fix eqWishboneS2M bug #157

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7564a1a
`sampleUnfiltered` respect `ExpectOptions`
lmbollen Jun 27, 2025
8150eae
`eqWishboneS2M`dont check `readData` on `err`
lmbollen Jul 2, 2025
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15 changes: 10 additions & 5 deletions clash-protocols/src/Protocols/Wishbone/Standard/Hedgehog.hs
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Original file line number Diff line number Diff line change
Expand Up @@ -155,9 +155,13 @@ eqWishboneS2M (Read _ sel) s2mA s2mB =
case sameNat (Proxy @(DivRU (BitSize a) 8)) (Proxy @nBytes) of
Nothing -> C.errorX "eqWishboneS2M: nBytes is not divisible by 8"
Just Refl ->
let nullBytes = C.repeat (0 :: BitVector 8)
in s2mA{readData = mux (unpack sel) (bitCoerce s2mA.readData) nullBytes}
== s2mB{readData = mux (unpack sel) (bitCoerce s2mB.readData) nullBytes}
let
maskBytes wb = wb{readData = mux (unpack sel) (bitCoerce wb.readData) nullBytes}
nullBytes = C.repeat (0 :: BitVector 8)
in
if s2mA.acknowledge
then maskBytes s2mA == maskBytes s2mB
else s2mA{readData = ()} == s2mB{readData = ()}

-- Validation for (lenient) spec compliance
--
Expand Down Expand Up @@ -671,5 +675,6 @@ sampleUnfiltered ::
[(WishboneM2S addressWidth (BitSize a `DivRU` 8) a, WishboneS2M a)]
sampleUnfiltered eOpts manager subordinate =
takeWhileAnyInWindow (expectedEmptyCycles eOpts) hasBusActivity $
uncurry P.zip $
observeComposedWishboneCircuit manager subordinate
P.take eOpts.eoSampleMax $
uncurry P.zip $
observeComposedWishboneCircuit manager subordinate
16 changes: 8 additions & 8 deletions clash-protocols/tests/Tests/Protocols/Wishbone.hs
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ import Hedgehog
import Hedgehog.Gen qualified as Gen
import Hedgehog.Range qualified as Range
import Protocols
import Protocols.Hedgehog (defExpectOptions)
import Protocols.Hedgehog (defExpectOptions, eoSampleMax)
import Protocols.Wishbone
import Protocols.Wishbone.Standard
import Protocols.Wishbone.Standard.Hedgehog
Expand Down Expand Up @@ -87,7 +87,7 @@ prop_addrReadIdWb_model =
property $
withClockResetEnable clockGen resetGen enableGen $
wishbonePropWithModel @System
defExpectOptions
defExpectOptions{eoSampleMax = 10_000}
addrReadIdWbModel
addrReadIdWb
(genData $ genWishboneTransfer @10 (Range.constantBounded) genDefinedBitVector)
Expand Down Expand Up @@ -141,7 +141,7 @@ prop_memoryWb_model =
property $
withClockResetEnable clockGen resetGen enableGen $
wishbonePropWithModel @System
defExpectOptions
defExpectOptions{eoSampleMax = 10_000}
memoryWbModel
(memoryWb (blockRam (C.replicate d256 0)))
(genData (genWishboneTransfer @8 (Range.constantBounded) genSmallInt))
Expand Down Expand Up @@ -179,7 +179,7 @@ prop_addrReadId_validator = property $ do
circuitSignalsN =
withClockResetEnable @System clockGen resetGen enableGen $
let
driver = driveStandard @System @(BitVector 8) @8 defExpectOptions reqs
driver = driveStandard @System @(BitVector 8) @8 defExpectOptions{eoSampleMax = 10_000} reqs
addrRead = addrReadIdWb @System @8
in
evaluateUnitCircuit
Expand All @@ -198,7 +198,7 @@ prop_memoryWb_validator = property $ do
circuitSignalsN =
withClockResetEnable @System clockGen resetGen enableGen $
let
driver = driveStandard @System @(BitVector 8) @8 defExpectOptions reqs
driver = driveStandard @System @(BitVector 8) @8 defExpectOptions{eoSampleMax = 10_000} reqs
memory = memoryWb @System @(BitVector 8) @8 (blockRam (C.replicate d256 0))
in
evaluateUnitCircuit
Expand All @@ -221,7 +221,7 @@ prop_addrReadId_validator_lenient = property $ do
circuitSignalsN =
withClockResetEnable @System clockGen resetGen enableGen $
let
driver = driveStandard @System @(BitVector 8) @8 defExpectOptions reqs
driver = driveStandard @System @(BitVector 8) @8 defExpectOptions{eoSampleMax = 10_000} reqs
addrRead = addrReadIdWb @System @8
in
evaluateUnitCircuit
Expand All @@ -240,7 +240,7 @@ prop_memoryWb_validator_lenient = property $ do
circuitSignalsN =
withClockResetEnable @System clockGen resetGen enableGen $
let
driver = driveStandard @System @(BitVector 8) @8 defExpectOptions reqs
driver = driveStandard @System @(BitVector 8) @8 defExpectOptions{eoSampleMax = 10_000} reqs
memory = memoryWb @System @(BitVector 8) @8 (blockRam (C.replicate d256 0))
in
evaluateUnitCircuit
Expand All @@ -260,7 +260,7 @@ prop_specViolation_lenient = property $ do
circuitSignalsN =
withClockResetEnable @System clockGen resetGen enableGen $
let
driver = driveStandard @System @(BitVector 8) @8 defExpectOptions reqs
driver = driveStandard @System @(BitVector 8) @8 defExpectOptions{eoSampleMax = 10_000} reqs
invalid = invalidCircuit
in
evaluateUnitCircuit
Expand Down