Verilog: collection of array tests

regression/verilog/arrays/array1.sv

@@ -7,10 +7,12 @@ module main;
   reg [7:0] my_array4[-10:-1];
 
   // Icarus Verilog says 8, but that's wrong.
-  always assert p0: ($bits(my_array0) == 8*10);
-  always assert p1: ($bits(my_array1) == 8*10);
-  always assert p2: ($bits(my_array2) == 8*10);
-  always assert p3: ($bits(my_array3) == 8*10);
-  always assert p4: ($bits(my_array4) == 8*10);
+  initial begin
+    p0: assert ($bits(my_array0) == 8*10);
+    p1: assert ($bits(my_array1) == 8*10);
+    p2: assert ($bits(my_array2) == 8*10);
+    p3: assert ($bits(my_array3) == 8*10);
+    p4: assert ($bits(my_array4) == 8*10);
+  end
 
 endmodule

regression/verilog/arrays/array_literal1.desc → regression/verilog/arrays/assignment_pattern2.desc

@@ -1,5 +1,5 @@
 CORE
-array_literal1.sv
+assignment_pattern2.sv
 --bound 0
 ^EXIT=0$
 ^SIGNAL=0$

regression/verilog/arrays/assignment_pattern2.sv

@@ -0,0 +1,8 @@
+module main;
+
+  reg [7:0] my_array[10] = '{1, 2, 3, 4, 5, 6, 7, 8, 9, 10};
+
+  p0: assert final (my_array[0] == 1);
+  p1: assert final (my_array[9] == 10);
+
+endmodule

regression/verilog/arrays/assignment_pattern3.desc

@@ -0,0 +1,8 @@
+CORE
+assignment_pattern3.sv
+
+^file .* line 3: number of expressions does not match number of array elements$
+^CONVERSION ERROR$
+^EXIT=2$
+^SIGNAL=0$
+--

regression/verilog/arrays/assignment_pattern4.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+assignment_pattern4.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+This does not parse.

regression/verilog/arrays/assignment_pattern4.sv

@@ -0,0 +1,16 @@
+module main;
+
+  int my_array[10] = '{ 1: 1, 2: 2, 3: 0, default: 10 };
+
+  p0: assert final (my_array[0] == 10);
+  p1: assert final (my_array[1] == 1);
+  p2: assert final (my_array[2] == 2);
+  p3: assert final (my_array[3] == 0);
+  p4: assert final (my_array[4] == 10);
+  p5: assert final (my_array[5] == 10);
+  p6: assert final (my_array[6] == 10);
+  p7: assert final (my_array[7] == 10);
+  p8: assert final (my_array[8] == 10);
+  p9: assert final (my_array[9] == 10);
+
+endmodule

regression/verilog/arrays/packed_direction1.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+packed_direction1.sv
+--module main
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+This gives the wrong answer.

regression/verilog/arrays/packed_direction1.sv

@@ -0,0 +1,13 @@
+module main;
+
+  bit [0:4][31:0] my_array1;
+  bit [4:0][31:0] my_array2;
+
+  initial begin
+    my_array1 = '{ 1, 2, 3, 4, 5 };
+    my_array2 = '{ 1, 2, 3, 4, 5 };
+    p1: assert(my_array1[0] == 1);
+    p2: assert(my_array2[0] == 5);
+  end
+
+endmodule

regression/verilog/arrays/packed_typedef1.sv

@@ -3,6 +3,6 @@ module main;
   typedef bit my_bit;
   my_bit [7:0] my_vector;
 
-  always assert p0: ($bits(my_vector) == 8);
+  initial p0: assert($bits(my_vector) == 8);
 
 endmodule

regression/verilog/arrays/unpacked_direction1.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+unpacked_direction1.sv
+--module main
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+This gives the wrong answer.

regression/verilog/arrays/unpacked_direction1.sv

@@ -0,0 +1,16 @@
+module main;
+
+  int my_array0[5];
+  int my_array1[0:4]; // same as [5]
+  int my_array2[4:0];
+
+  initial begin
+    my_array0 = '{ 1, 2, 3, 4, 5 };
+    my_array1 = '{ 1, 2, 3, 4, 5 };
+    my_array2 = '{ 1, 2, 3, 4, 5 };
+    p0: assert(my_array0[0] == 1);
+    p1: assert(my_array1[0] == 1);
+    p2: assert(my_array2[0] == 5);
+  end
+
+endmodule