Verilog: fix array index direction for descending and ascending ranges

[kroening]

Arrays declared with descending ranges (e.g., [4:0]) or ascending ranges with non-zero offsets were not correctly mapping Verilog indices to internal array indices. This affected both packed and unpacked arrays.

Problem

For a descending range like int my_array[4:0], the assignment pattern '{ 1, 2, 3, 4, 5 } should assign index 4=1, index 3=2, ..., index 0=5 per IEEE 1800-2017 §10.9.1. However, my_array[0] was returning 1 instead of 5 because no index adjustment was performed.

The same issue affected packed arrays like bit [4:0][31:0].

Fix

• Unpacked arrays: Adjust the Verilog index to the internal index in convert_bit_select_expr() based on range direction and offset.
• Packed arrays: Reverse assignment pattern operands for descending ranges so that internal index 0 corresponds to Verilog index 0. Update to_bitvector() in the lowering to match the new convention.
• Packed array types: Set ID_C_increasing on multi-dimensional packed array types (was previously missing).

Test updates

• packed_direction1 and unpacked_direction1: promoted from KNOWNBUG to CORE
• array_conversion3: updated expectations from REFUTED to PROVED
• array_in_struct1: corrected assertions to match IEEE 1800-2017 descending range semantics