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Update exitcode from invalidSyscall to illegalInstruction #134

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Merged
merged 2 commits into from
Jan 22, 2025
Merged

Update exitcode from invalidSyscall to illegalInstruction #134

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cfd156c
Change exit code from invalidSyscall to invalidInstruction for reserv…
mininny Jan 21, 2025
740e8f3
Change exit code from invalidSyscall to invalidInstruction for invali…
mininny Jan 21, 2025
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6 changes: 3 additions & 3 deletions rvgo/fast/vm.go
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Original file line number Diff line number Diff line change
Expand Up @@ -590,7 +590,7 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {

// bits[14:12] set to 111 are reserved
if eq64(funct3, byteToU64(0x7)) != 0 {
revertWithCode(riscv.ErrInvalidSyscall, fmt.Errorf("illegal instruction %d: reserved instruction encoding", instr))
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction %d: reserved instruction encoding", instr))
}

imm := parseImmTypeI(instr)
Expand Down Expand Up @@ -688,13 +688,13 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
case 1: // 001 = SLLIW
// SLLIW where imm[5] != 0 is reserved
if and64(imm, byteToU64(0x20)) != 0 {
revertWithCode(riscv.ErrInvalidSyscall, fmt.Errorf("illegal instruction %d: reserved instruction encoding", instr))
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction %d: reserved instruction encoding", instr))
}
rdValue = mask32Signed64(shl64(and64(imm, byteToU64(0x1F)), rs1Value))
case 5: // 101 = SR~
// SRLIW and SRAIW where imm[5] != 0 is reserved
if and64(imm, byteToU64(0x20)) != 0 {
revertWithCode(riscv.ErrInvalidSyscall, fmt.Errorf("illegal instruction %d: reserved instruction encoding", instr))
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction %d: reserved instruction encoding", instr))
}
shamt := and64(imm, byteToU64(0x1F))
switch shr64(byteToU64(5), imm) { // top 7 bits select the shift type
Expand Down
6 changes: 3 additions & 3 deletions rvgo/slow/vm.go
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Expand Up @@ -774,7 +774,7 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err

// bits[14:12] set to 111 are reserved
if eq64(funct3, byteToU64(0x7)) != (U64{}) {
revertWithCode(riscv.ErrInvalidSyscall, fmt.Errorf("illegal instruction %d: reserved instruction encoding", instr))
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction %d: reserved instruction encoding", instr))
}

imm := parseImmTypeI(instr)
Expand Down Expand Up @@ -872,13 +872,13 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
case 1: // 001 = SLLIW
// SLLIW where imm[5] != 0 is reserved
if and64(imm, byteToU64(0x20)) != (U64{}) {
revertWithCode(riscv.ErrInvalidSyscall, fmt.Errorf("illegal instruction %d: reserved instruction encoding", instr))
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction %d: reserved instruction encoding", instr))
}
rdValue = mask32Signed64(shl64(and64(imm, byteToU64(0x1F)), rs1Value))
case 5: // 101 = SR~
// SRLIW and SRAIW imm[5] != 0 is reserved
if and64(imm, byteToU64(0x20)) != (U64{}) {
revertWithCode(riscv.ErrInvalidSyscall, fmt.Errorf("illegal instruction %d: reserved instruction encoding", instr))
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction %d: reserved instruction encoding", instr))
}
shamt := and64(imm, byteToU64(0x1F))
switch shr64(byteToU64(5), imm).val() { // top 7 bits select the shift type
Expand Down
6 changes: 3 additions & 3 deletions rvsol/src/RISCV.sol
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Original file line number Diff line number Diff line change
Expand Up @@ -1161,7 +1161,7 @@ contract RISCV is IBigStepper {
// LB, LH, LW, LD, LBU, LHU, LWU

// bits[14:12] set to 111 are reserved
if eq64(funct3, toU64(0x7)) { revertWithCode(0xf001ca11) }
if eq64(funct3, toU64(0x7)) { revertWithCode(0xbadc0de) }

let imm := parseImmTypeI(instr)
let signed := iszero64(and64(funct3, toU64(4))) // 4 = 100 -> bitflag
Expand Down Expand Up @@ -1295,12 +1295,12 @@ contract RISCV is IBigStepper {
// 001 = SLLIW

// SLLIW where imm[5] != 0 is reserved
if and64(imm, toU64(0x20)) { revertWithCode(0xf001ca11) }
if and64(imm, toU64(0x20)) { revertWithCode(0xbadc0de) }
rdValue := mask32Signed64(shl64(and64(imm, toU64(0x1F)), rs1Value))
}
case 5 {
// SRLIW and SRAIW where imm[5] != 0 is reserved
if and64(imm, toU64(0x20)) { revertWithCode(0xf001ca11) }
if and64(imm, toU64(0x20)) { revertWithCode(0xbadc0de) }

// 101 = SR~
let shamt := and64(imm, toU64(0x1F))
Expand Down
4 changes: 2 additions & 2 deletions rvsol/test/RISCV.t.sol
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Expand Up @@ -2487,7 +2487,7 @@ contract RISCV_Test is CommonTest {
state.registers[25] = 0xf956;
bytes memory encodedState = encodeState(state);

vm.expectRevert(hex"00000000000000000000000000000000000000000000000000000000f001ca11");
vm.expectRevert(hex"000000000000000000000000000000000000000000000000000000000badc0de");
riscv.step(encodedState, proof, 0);
}

Expand All @@ -2501,7 +2501,7 @@ contract RISCV_Test is CommonTest {

bytes memory encodedState = encodeState(state);

vm.expectRevert(hex"00000000000000000000000000000000000000000000000000000000f001ca11");
vm.expectRevert(hex"000000000000000000000000000000000000000000000000000000000badc0de");
riscv.step(encodedState, proof, 0);
}

Expand Down
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