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Pull requests: llvm/circt

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Pull requests list

[MooreToCore]Fix a crash caused by block args as observed values for llhd.wait. Moore
#8210 opened Feb 8, 2025 by hailongSun2000 Loading…
4
[Pipeline] Extend Pipeline Dialect's pipeline-schedule-linear pass to support more types of scheduling problems
#8209 opened Feb 8, 2025 by bubblepipe42 Loading…
[Verif] Mark SymbolicValueOp result as MemAlloc verif
#8208 opened Feb 7, 2025 by fabianschuiki Loading…
1
[ESI][BSP] Simple ToHost DMA engine ESI
#8207 opened Feb 7, 2025 by teqdruid • Draft
[MooreToCore] Properly deal with OOB access in dyn_extract Moore
#8201 opened Feb 7, 2025 by maerhart Loading…
5
[FIRRTL] Add folders for add and mul
#8200 opened Feb 7, 2025 by mtsokol Loading…
5
[RTG][InlineSequences] Support interleave_sequences RTG Involving the `rtg` dialect
#8199 opened Feb 7, 2025 by maerhart Loading…
[RTG][Elaboration] Support interleave_sequences, factor our sequence inlining and label resolution RTG Involving the `rtg` dialect
#8198 opened Feb 7, 2025 by maerhart Loading…
[RTG][Elaboration] Use malloc instead of IR for virtual registers and labels RTG Involving the `rtg` dialect
#8194 opened Feb 5, 2025 by maerhart Loading…
[RTG] Add interleave_sequences op RTG Involving the `rtg` dialect
#8189 opened Feb 4, 2025 by maerhart Loading…
[RTG] Custom assembly format for 'rtg.test' operation RTG Involving the `rtg` dialect
#8188 opened Feb 4, 2025 by maerhart Loading…
[RTG] Add the PyRTG frontend RTG Involving the `rtg` dialect
#8187 opened Feb 4, 2025 by maerhart Loading…
5
[FIRRTL] Add Clock Switch intrinsic
#8183 opened Feb 3, 2025 by darthscsi • Draft
1
[COMB] Get rid of "bin" flag in comb.
#8180 opened Feb 3, 2025 by darthscsi • Draft
3
[firtool] Add an option to emit HW MLIR into file
#8169 opened Feb 1, 2025 by uenoku Loading…
7
[RTG][Elaboration] Add support for context operations RTG Involving the `rtg` dialect
#8151 opened Jan 30, 2025 by maerhart Loading…
[RTG] Add on_context and context_switch operations RTG Involving the `rtg` dialect
#8150 opened Jan 30, 2025 by maerhart Loading…
[HW] Start of high imedence operations and types
#8134 opened Jan 28, 2025 by darthscsi Loading…
6
[FIRRTL][CAPI] add layer for firrtlTypeGetRef
#8093 opened Jan 17, 2025 by sequencer Loading…
[RTG][python] fix populateDialectRTGTestSubmodule namespacing
#8078 opened Jan 13, 2025 by makslevental Loading…
3
[HW] Add passes to remove modules from the hierarchy and recursively expose IO of their instances
#8070 opened Jan 12, 2025 by CircuitCoder Loading…
1 task
6
Convert ICE40 to BLIF
#8031 opened Jan 5, 2025 by darthscsi • Draft
[ImportVerilog] add real literal support, refine real type, and add real format support Moore
#8020 opened Dec 29, 2024 by chenbo-again • Draft
6
Add the BLIF dialect.
#8019 opened Dec 29, 2024 by darthscsi Loading…
4
Add the ICE40 dialect.
#8018 opened Dec 27, 2024 by darthscsi Loading…
11
ProTip! Updated in the last three days: updated:>2025-02-05.