Currently the I/O registers are allocated in one big block using their relative locations on the ATmega series. This makes the core unsuitable for emulating ATtiny MCUs, in which the I/O registers have very different addresses. (There is an ATtiny15 device, but is and always has been an unused stub.)
Currently the I/O registers are allocated in one big block using their relative locations on the ATmega series. This makes the core unsuitable for emulating ATtiny MCUs, in which the I/O registers have very different addresses. (There is an ATtiny15 device, but is and always has been an unused stub.)